SU680200A1 - Gating signal shaper - Google Patents

Description

(54) FORMING STROBE SISHALS

A second counter, a second digital comparator, the second input of which is connected to the output of the second memory block, is fed to the input of this block by a code of the vertical coordinate, while the synchro pulses are fed to the counting input of the second counter, and the HR sync pulses, the first trigger connected in series, the horizontal component of the strobe signal, the first decoder, the first element of the PLM, and the first inverter, as well as the connected second trigger, the second element OR and the second inverter, the first input of the first trigger is connected to the output of the first digital comparator, the second input of the first trigger, the input of the mouth block - the initial state of the first counter 20 is connected to the second internal unit - the first OR element and to the installation input of the counter of the horizontal component of the gate signal, lia whose counting input is supplied with clock pulses , the first input of the second trigger is connected to the output of the second digital comparator, the second input of the second trigger is connected to the output of the second inverter, the input of the unit for setting the initial state of the second counter is connected to the second input of the second OR element and

the installation input of the counter of the vertical component of the strobe signal, to the counting input of which the lower-order clock pulses are fed, the second and third inputs of the And element are connected respectively to the output of the first of the 5th second triggers.

The drawing shows a structural electrical circuit of the proposed driver.

The strobe driver includes a first memory block 1, a first digital 40 comparator 2, a first counter 3, a block 4 for setting the initial state of the first counter, a first trigger 5, a counter 6 for the horizontal component of the strobe signal, the first decoder 7, the first element OR 8, the first inverter 45 9, element 10, the second trigger 11, the counter 12 of the vertical gate signal, the second decoder 13, the second element OR 14, the second inverter 15, the second memory block 16, the second digital comparator 17, the second §0 counter 18 and block 19 Settings initial state of the second counter.

The shaper works as follows.

The memory blocks 1 and 16 store the gualn 55 and the object coordinates that are updated once in each frame. Digital comparators 2 and 17 compare the coordinate codes stored in memory blocks 1 and 16, respectively, with the instantaneous values of the codes on

counters 3 and 18. The counting input of the first counter 3 receives clock pulses, and the counter 1P. The input of the second counter 18 is lowercase clock pulses. If the codes on the first counter 3 and the first memory block 1 (similar to the second memory block 16 and the second counter 18) are equal, a pulse occurs at the output of the first digital comparator 2 (respectively, the second digital comparator 17). On counters 3 and 18, in the re-run interval of the reawater, using blocks 4 and 19 for setting the initial state of the first and second counters 3 and 18, a code of a number equal to half the size of the gating pulse expressed in the number of nominal decomposition elements is set. As a result, the output pulses of digital comparators 2 and 17 are ahead in time of the video signal of the object by a fixed number of decomposition elements equal to half the duration of the gating pulse.

The output pulses of digital comparators 2 and 17 are fed to the installation inputs of the unit of the flip-flops 5 and 11 corresponding. Set to one, trigger 5 enables the counting, counter 6, the counting input of which receives clocks (e pulses, 1 an input of the zero setting - horizontal sync pulses. When dialing on the counter 6, equal to the size of the strobing horizontally, the output connected to the counter With the pin 6 of the decoder 7, a pulse is generated, coming through the first element OR 8 and the first inverter 9 to the input of the zero setting of the trigger 5, setting the trigger to zero and thus prohibiting further advancement of the counter 6.

In the flyback interval on the line, the horizontal sync pulse sets the counter 6 to zero and confirms the zero state of the trigger 5, the first element OR 8 and the first inverter 9 pass. This confirmation is necessary to eliminate the ambiguity of the trigger state when the power is turned on. The output of the trigger 5 is also connected to the second input of the element 10, the third input of which is connected to the output of the second trigger 11, and the first input is a video signal that passes to the output of the element 10 only if there are resolution potentials on the second and third inputs simultaneously.

The operation of the generator of the vertical component of the strobe signal, i.e. the second trigger II of the counter 12, the second decoder 13, the second element OR 14 and the second inverter 15 are similar to the described operation of the horizontal component generator. The counting input of the counter 12 receives the lower-case sync pulses, the input clock of the zero-setting of the counter 12 and the second input of the second element OR 14 receive frame sync pulses.

Claims (1)

1. Application No. 2373499 / 18-09, according to which a decision was made to issue an author's certificate, H 04 N 5/06, 1976. Pulsed pulses