SU1427565A1 - Device for monitoring a-d converters - Google Patents

Abstract

The invention relates to instrumentation and can be used to control the hysteresis and drift of analog-to-digital converters. The purpose of the invention is to expand the scope. To do this, a device containing integrator 2, block 4 of code comparison, the first and second counters 9, 11 pulses, the first element 12, the first and second triggers 24, 19, the 3 clock pulse generator, the third counter 10 pulses, multiplexer 22, source 1 constant voltage, three switches 15-17, T-trigger 18, element I 20, shaper 21 pulses, which made it possible to estimate the instability of analog-to-digital converters. 1 PC. s (c

Description

The invention relates to instrumentation engineering and can be used to monitor the accuracy parameters of analog-to-digital converters (ADCs).

The aim of the invention is to expand the scope of application due to the possibility of assessing the instability.

4275652

the N / -1 code is set at the output of the ADC to the lower level U of the transition zone of the N / Ny-1 codes, and code comparison block 4 returns to the zero state at its output. Thereby, at the output of block 4, a pulse is formed, the pulse of which is proportional to the hysteresis value in the jth

Nosti ADC.

The drawing shows the functional diagram of the device.

The device contains a source of constant voltage 1, integrator 2,

The 3 clock pulse generator, unit 15 switches the polarity of the reference code 4 comparison codes, input bus 5, output bus 6, bus 7 reference code, input bus 8 Start, counters 9-11 pulses, elements 12-14, switches 15-17 T trigger 18, ES trigger 19, element OR 20, driver 21 pulses, multiplexer; 22 control bus 23, RS trigger; 24, bus 25 Measurement result.

the voltage on the input of the integrator 2, and the process is repeated further, with the output of block 4 producing pulses, the duration of which is 20 1. is proportional to the hysteresis Hj. at the j-th point of the ADC characteristics

tl H / tgoL. With the arrival of the impulse. With the output device, the next m-25 block 4 is working on the counting input of the counter

at once.

The pulse pulse counter 11 pulses are preliminarily delivered to the Start bus B, and the integrator 2-, T-trigger 18 and counters 9 and 10 pulses are zeroed through the OR 20 element. On the bus 7 of the reference code, the NJ code of the jth point of the conversion characteristic of the monitored ADC is set, thereby preparing the device for the Measurement mode. On the falling edge of the zeroing pulse, integrator 2 begins to integrate the positive reference voltage of the surge generator.

point 1, arriving at the input with the integration T at the output of the trigger 19. rator 2 through the switches 15 and 17. . At the same time, the voltage at the output of the integrator 2 increases according to a linear law with the angle of inclination to the time axis t and the code N at the output of the ADC changes accordingly. Upon reaching the output voltage, the integrator 2 of the upper level U of the transition zone of the NJ / N / -1 codes at the output of the ADC zeroed the code. At this moment, 45

The leading edge of this pulse is formed on the front of the overflow pulse from the output of the pulse counter 9, and the rear edge is formed on the leading edge of the overflow pulse of the pulse counter 10, which in the specified interval counts the pulses taken; from the generator output 3 clock pulses, i have; their constant period and duration. Consequently

The unit 4 is triggered. Comparison of the time interval T

It installed a 1-RS trigger 24 into one state and switched the switches 16 and 17 on the polarity of the reference voltage at the input of the integrator 2, the output voltage of which begins to decrease with a speed also determined by the angle 6. At the moment of equality of this tension

10 point conversion characteristics

. ADC.

t, h, / tgJL. Zero state of block 4 again

the voltage on the input of the integrator 2, and the process is repeated further, with the output of block 4 producing pulses, the duration of which is 1. proportional to the hysteresis Hj. at the j-th point of the ADC characteristics

tl H / tgoL. With the arrival of the impulse .c output0

9 pulses last overflow, and the overflow signal from its output resets the KZ-trigger-24 state to zero, the forward output of which thus produces a pulse, the duration of which T, is directly proportional to the average value of the H -f hysteresis in the jth ADC characteristic point

T. 2

2 (2-11 t.) H; cf

 tg (. 4 tg ".

iclx, -1

After the formation of impulse duration. T a pulse of duration T is formed at the output of the trigger 19..

The leading edge of this pulse is formed on the front of the overflow pulse from the output of the pulse counter 9, and the rear edge is formed on the leading edge of the overflow pulse of the pulse counter 10, which in the specified interval counts the pulses taken; from the generator output 3 clock pulses, i have; their constant period and duration. Consequently,

time interval T does not depend on

The hysteresis of the A / D converter is strictly constant, depending only on the capacitance of the counter 10 pulses, which can be made arbitrarily large.

At the time specified interval T pulse from the direct output of the trigger 19 using the switch 15, the integrator 2 remembers the value corresponding to the last operation of block 4 comparison codes.

During time T, an j-ro transition of the A / D converter may occur due to its own drift, therefore after the interval T has elapsed, the switch 15 switches, and the code comparison unit 4 is set to the state that the switches 16 and 17 make so that the output voltage integrator 2 rushes to the corresponding value of U ;, Ut of the hysteresis zone. it

the time coming after the pause (TA interval) will be the time proportional to the ADC instability at the corresponding jth point of the conversion characteristic. Further, the process is similar to the process on the interval T / t.

On the falling edge of the d-pulse, T is set to the single state of the RS flip-flop 24, if at the beginning of the pause Tj n - the voltage at the output of the integrator 2 is more pronounced than at the end of this pause due to the ADC drift. If, on the contrary, the RS flip-flop 24 is set to one with some delay, determined by the departure of the ADC conversion characteristic in the opposite direction.

A positive pulse at the forward output of the RS flip-flop 19 is generated at the instant of the appearance of an overflow pulse from the output of the pulse counter 9 pulses. The duration T of this pulse can be represented as follows.

Тз Т, + Т, -HTj, Т

Where

time proportional to the care of a controlled ADC.

These time intervals are converted into the number of pulses using the master oscillator 3, the elements 12 and 13. Thus, the output of the element 12 during the measurement time passes the number of pulses proportional to T, i.e. hysteresis, and the output of the element And 13 comes the number of pulses proportional to time, i.e. the amount of hysteresis and drift.

Depending on the control code of the bus 23, the multiplexer 22 transmits to the input of the counter 11 a number of pulses proportional to either the time interval T or the time interval.

20

five

15, 755.

The device then returns to its original state at the moment when the second overflow pulse appears at the output of the counter 9. In this case, the KZ trigger 24 and T-trigger 18 are set to the zero state; On the falling edge of the pulse at the forward output of the T-flip-flop 18, the former 21 forms a reset pulse for integrator 2 and counters 9 and 10.

At the end of this pulse, the counter 10 during the overflow interval T., sets the RS flip-flop 19 to the zero state.

Thus, to measure the hysteresis and leave the j-ro junction of the A / D converters on bus 23 of multiplexer 22, first set the code corresponding to obtaining information on the hysteresis, and then restarting on bus 23, the control code to obtain information on hysteresis and care.

The final information about the instability of the j-ro junction of the ADC semi1: a y by simply subtracting the first value recorded in counter 11 (, from the second.

Claims (1)

Claims. An analog-to-digital converter control device containing an integrator, the output of which is an output bus. The first element And, the second input of which is connected to the direct output of the first RS trigger, the R input of which is connected to the overflow output of the first pulse counter, the counting input of which is combined with the S input of the first RS grigger and connected , the first inputs of which are the input bus, and the second - the reference code bus, the outputs of the second pulse counter are the output bus Measurement result, which is characterized by the fact that a constant voltage source, three switches, a multiplexer, a T-flip-flop, a second and the third AND element, the OR element, the pulse shaper, and the third pulse counter, the overflow output of which is connected to the R input of the second H3 flip-flop, the installation input in O is combined with the installation inputs in O of the first pulse counter, T-trigger and integrator and connected to the output of the OR element, the first input of which is combined with the installation input O of the second pulse counter and is the input bus Start, and the second input through the pulse shaper is combined with the first input of the second element AND and is connected to the forward output of the T-flip-flop inv The pc output of which is connected to the third input of the first element I, the output of which is connected to the first information input of the multiplexer, the output of which is connected to the counting input of the second pulse counter, the control input of the multiplexer is the control input bus, the second information input is connected to the k output of the second element And, the second input is connected to an inverse code of the second RS trigger, and the third input is combined with the first input of the third element I and connected to the output of the clock generator, the counting input of the third pulse counter connected to the output of the third element I, the second input of which is combined with the control input of the first switch and is connected to the forward output of the second RS trigger, the S input of which is combined with the T input of the T trigger and connected to the overflow output of the first pulse counter, the counting input of which is connected to the control inputs of the second and t the second switches, the first and second inputs of which are pairwise combined and connected to the corresponding outputs of a DC voltage source, while the output of the second switch is connected to the first input of the first switch and is a 1-point zero potential; the output of the third switch is connected to the second input of the first switch, the output of which is connected to the input of the integrator.