SU602940A1 - Number comparing arrangement - Google Patents

Description

(54) DEVICE FOR. COMPARISON NUMBERS

On Tines 11 and 12 at the same time, that is, at each time point, bits of the first and second operands with the same weights are sent to the cables.

In the initial state, the subtraction unit and the device triggers are set to the zero state. If it is necessary to determine the maximum of two numbers, by the beginning of the first cycle of calculations, a signal arrives at bus 13 and goes through control unit 5 to the circuit issuing a direct high-order code for subtractor I. This signal remains intact until the device ends. Thus, at the outputs of the high bit of subtractor 1, before the end of operation of the device, there is a direct code of the high bit of the subtractor. If it is necessary to determine the minimum of two numbers, then a similar signal is fed to bus 14 and through the control node 5 to the output circuit of the return code CTapinero of subtracting unit 1. To the beginning of each i-ro calculation cycle (1 1, 2, .. ., t), the next bits of the buses 11 and 12 are received, respectively, a / and c, which retain their value until the end of the calculation cycle. In each cycle of calculations, clock buses 15, 16, and 17 alternately receive clock signals Yi 2 and YJ, respectively. In the first cycle of the calculation cycle, the clock signal from bus 15 goes to the receive circuit of the trigger code 7, and to control the input of the adder modulo two 6 and through the control unit 5 to the shift circuit of the subtraction unit 1. In this case, the trigger 7 receives a code from the output older than the discharge of the subtraction unit 1 (remembering the sign of the previous balance), the summation of the second and third bits of the subtraction unit 1 and shift the contents of the block 1 for one bit to the left (simultaneous reception of the code from subtractor 1, analysis of the bits of this block and shift of the block contents are possible, since the block of subtraction 1 is moving, and therefore, each bit of subtractor 1 must be built on a pair triggers or on triggers with internal delay).

Suppose that, as a result of summation, the signal at the output of summator 6 is not according to wils. In this case, trigger 8 does not change its initial state. Then, in the second cycle of the computing cycle, the bus 16 receives a signal to the input of the control unit 5, the second output of which receives a signal to the receive circuit of the code of subtraction unit 1. As a result, the contents of subtractor 1 and apply the discharge code a. The first operand is subtracted by the bit code 5 / of the second operand. In the third clock cycle, the clock bus 17 receives a signal to the circuit issuing the trigger code 7. As a result, depending on the condition of trigger 7 and the code on the high bit of the subtractor (i.e., depending on the previous and present signs of the remainder ), the adder code a is transmitted to the adder 2 through the switch 4. or count bit 0, and through switch 3 through cnina.iaM with

the outputs of the AND 9 and 10 elements are transmitted, respectively, the reverse or direct code from the iibixids of subtraction unit 1, or in the absence of signals at the outputs of the elemen tary elements 9 and 10, this code 5 is not transmitted. In this case, if the trigger 7 and the code at the output of the higher bit of the block of Vincani 1 have the value O, then the code a / is transmitted through the switch 4, and the code is not transmitted through the switch 3. If their status is O and 1, respectively, then switch 4 transmits code a, -, and switch 3 - inverse code of subtraction unit 1. For states 1 and O, respectively, switch 4 transmits the code to ;, and com.mutator 3 - direct subtraction unit code 1. As a result of this, AA output of adder 2, the discharge code C appears; result operand.

Suppose now that in the first cycle of calculations as a result of the summation by the adder 6 of the second and third bits of the subtractor 1 at the output of the adder 6, the signal was received. This means that the difference between the numbers is so great that the subsequent bits cannot change the ratio between the numbers. Therefore, there is no need to carry out calculations in subtraction unit 1, and it suffices to transmit the discharge codes of the corresponding

5 operand directly from the operand bus to the device output. The signal from the output of the adder 6 enters the single input of the trigger 8 and sets it to the single state. As a result, the signal is removed from the inverted output of the trigger 8 and, as a result, there are no signals at the first inputs of elements P 9 and 10 (codes from the outputs of subtraction unit 1 are not transmitted) and at the control input of the control unit 5 (signals to the control inputs of subtraction 1 does not arrive and it does not change its state further, and the code does not arrive at the outputs of the higher bit of subtraction unit 1). If trigger 7 is set to the zero state, then co.mutator 4 transmits the code a,., For all the first cycles, and if it is in the unit state, then the code in ;. Since the code at the output of the higher bit of subtractor 1 is absent, trigger 7 does not change its state in the future. This ends one cycle of calculations. Esc operands have difference. M. Then it is necessary to perform m calculation cycles.

Thus, the proposed device allows the comparison of the numbers represented by the binary redundant code.

Claims (2)

1. USSR author's certificate number 441560, cl. G 06 F 7/04, 1972. 2..Avtorskoe certificate of the USSR № 446055, cl. G 06 F 7/04, 1973.