SU983707A1 - Elementary function computing device - Google Patents

Description

(5) DEVICE FOR CALCULATION OF ELEMENTARY FUNCTIONS

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The invention relates to computing and can be used in the development of specialized and universal computers, with the introduction of special commands like sin X, cos X, tg x, ctg x, arcsin x, e, In X, sh X, arsh x, (ifx) and the like.

A digital calculator of tangent and cotangent is known, which contains an I-bit argument register, a persistent storage device, a control unit, a multiplication unit, intermediate result registers, a divisor unit, OR elements, an output perHCTp lJ

A disadvantage of the known device is the impossibility of calculating hyperbolic, logarithmic and gyf functions.

The closest to the invention to the technical essence is a device for calculating an exponential function comprising two single-bit combinational subtractors, two accumulative registers, a one-way memory block, gates, a shift register, a pseudo-part sign determining unit, a convergence analysis block (comparison circuit , control unit, reset unit and iteration block 23.

A disadvantage of the known device is a narrow specialization. To create a processor that performs computations for trigonometric, circular, exponential, logarithmic, hyperbolic, and inverse hyperbolic functions, large hardware costs are required.

The aim of the invention is to expand the class of tasks to be solved due to the possibility of the device additionally calculating trigonometric, hyperbolic and logarithmic functions.

The goal is achieved in that a device for calculating elementary functions comprising two accumulator registers, an adder, a first multiplier, a comparison circuit, a reset pulse shaper, a control unit and a memory unit, the control inputs of the first and second accumulation registers are connected respectively to the first and the second outputs of the control unit, the third and fourth outputs of which are connected to the control inputs of the adder and the first multiplier, respectively, the output of which is connected to the information input the second accumulator register, the first information input of the adder and the first input of the comparison circuit, the output of which is connected to the first input of the control unit through the reset pulse shaper, the second information input and the output of the adder are connected respectively to the output and information input of the first accumulative register, the setup input of which is connected to the output of the second cumulative register and the first information input of the first multiplier, the second multiplier is additionally entered, the operation register , operation decoder, counter, switch, three memory blocks, constant register, pseudo-argument register and error register, the output of which is connected to the second input of the comparison circuit, the control inputs of the error register, second multiplier, counter, switch, constant register and pseudo argument register correspondingly with the fifth to the tenth outputs of the control unit, the second input of which is connected through the operation decoder to the output of the operation register, the output of the counter is connected to the information input of the switch, the outputs from the first the fourth one is connected to the inputs of the first to fourth memory blocks, respectively, the outputs of which are connected to the first information input of the register of constants, the second information input of which is connected to the output of the pseudo-argument register and the first information input of the second multiplier, the second information input of which is connected to the output of the register constants, the output of the second multiplier is connected to the information input of the pseudo-argument register, the output of which is connected to the installation input of the second cumulative p Giustra, second information input of the first multiplier is connected to the output of the second multiplier. .

Moreover, the control unit contains a pulse generator, a clock generator, three shift registers, five flip-flops, ten groups of AND elements, three OR elements and two AND elements, inputs of the first and second OR elements, and first inputs of AND elements with the first through fifth groups connected with the second input of the control unit, the output of the pulse generator is connected to the input of the sync pulse generator, the outputs from the first to the fourth of which are connected to the inputs of the third OR element, the output of which is connected to the synchronous inputs of the shift registers, od overflow sdvigd first register. connected to the first inputs of the first and second And elements, the second inputs of which are connected to the outputs of the corresponding OR elements, the output of the first And element is connected to the information input of the second shift register, the overflow output of which is connected to the information input of the third shift register and the output of the second And element, outputs bits from the first to the fifth third shift register with the first inputs respectively from the first to the fifth flip-flops the second inputs of which are connected to the first input of the control unit, the outputs The first and second bits of the first shift register are connected to the second inputs of the AND elements of the first and second groups, the output of the first trigger is connected to the second inputs of the AND elements of the third group, the third inputs of which are connected to the fourth output of the sync pulse generator, the output of the second trigger is connected to the second inputs of the elements And the fourth and fifth groups and the first inputs of the elements And the sixth group, the second inputs of which are connected to the first output of the clock generator, the third inputs of the elements And the fourth of the first and fifth groups and the first inputs of the elements of the seventh group, the second inputs of which are connected to the output of the fifth trigger, the fourth inputs of the elements of the fifth group are connected to the second output of the sync pulse generator, the fourth output is connected to the first inputs of the elements of the eighth group, the second inputs which are connected to the output of the third trigger., the output of the fourth Urigger is connected to the first inputs of the elements of the Ninth and the tenth groups, the second inputs of which are connected to the third output of the clock generator output The first bit of the first shift register is connected to the first, second, third, fourth, sixth and ninth outputs of the control unit, the third bit output of the first shift register is connected to the first output of the control unit, the bit outputs from the first to the third second shift register. connected to the ninth, sixth and tenth outlets of the control unit, the outputs of the elements of the first group are connected to the seventh output of the control unit, the second output of which is connected to the 1H of the elements of the second group, the output of the elements and the third group The plugs are connected to the eighth output of the control unit, the sixth output of which is connected to the outputs of the elements of the fourth and sixth groups, the outputs of the elements of And the fifth group are connected to the seventh output of the control unit, the fourth, second, third and first outputs of which are connected to the outputs of the elements And respectively the eighth, the ninth, tenth and seventh groups. FIG. 1 is a block diagram of the device; in fig. 2 - control unit; in fig. 3 -. timing charts of individual blocks. The device for calculating elementary functions contains a control block 1, an adder 2, multipliers 3 J, registers 5 and 6 accumulative, register 7 pseudo-arguments, register 8 constants, blocks 9-12 of memory, a switch .13. the counter 1, the 15-operation register, the decoder 16 of the operation, the error register 17, the comparison circuit 18, the reset pulse generator 19 and the device input 20. The control unit contains a pulse generator 21, a shaper 22 clock pulses, shift registers 23-25, triggers 26-30, groups of elements AND, elements OR, elements AND i and its. The timing diagram (Fig. 3) for the description of the operation of the device shows the following controls: - sync pulses at the output of the sync pulse (ci-ci, pulse start, reset pulse start signals of the first and second multipliers, adder , memory unit (Start UM-1, Start UM-2, Start :, Start ROM, the signals transfer the contents of one register to another, the signals of the result of multiplication and summing up or accumulative registers (Р7-гР6, Р6 -Г Р5, Р7 РЗ , UM-1 - P6, UM-2-P 7, X-P5), the signals to increase the counter content by one (+1 BIT), A shaper 19 is designed to convert a potential signal with cxef i 18 comparison, arriving at a given computational accuracy, into a pulse one, and outputting it to control unit 1 to reset the control unit triggers, and contains a single pulse generator (GOI and a reset signal distribution circuit. The signal distribution circuit; the reset yv delays the reset signals of the triggering triggers 29 and, 30 for the duration of the operation of the adder 2 and the transfer of the result of the summation from the adder to the register 5. Calculation of the functions in the proposed y This is based on the use of the Taylor series properties, which consist in the following: a) when calculating rows for different functions, they are performed with 6 K) 1e intermediate actions (this makes it possible to use the same block of one-sided memory for calculating different functions); b) the fast convergence of the series provides a small capacity of one-way memory blocks, TRIGOMOMETRIC, circular, exponential, logarithmic, hyperbolic, and inverse hyperbolic functions with the Taylor transformations can be written as an infinite step (known number). Taylor series, region; Esteems of convergence of series and practical ranges of changes in the argument X are shown in Table 1. To calculate the functions f (x) with a given error ik, it is necessary to calculate n the first members of the series. Y, &) the number of first members of the series, which must be taken into account when calculating, from the range of variation of the argument x and the specified calculation accuracy D are given in Table. Calculation of the functions given in table. 1, it is convenient to produce by the recurrent formulas of the form f (x)), (1) ,,. . where x,. - real values of the argument and the number of a member of a row, respectively; p and yyyy yaTg y f (x) - the value of the functions; and - the value of the 1st member p. „,. ,,. 1р (х), Ч (1Г - factors, depending on. 1 "(., Expressions for t |) (x) и) are given in Table. 3. For the functions in question, the recurrence relations, for example, for a fixed-point dual number system, have the form ex)., 4cxmo (Wty.) 4 (.) Where n, t, n1, t, t. - scale coefficients Uo U Ch l quenty for functions and arguments; f 1 if UQ 1 DO I t., if U ,, q (x). The ranges of variation of the real values of functions and arguments and the corresponding scales are given in. tab. C, where A is the value that determines the range of variation of the real values of the function f (x), B determines the range of variation of the value of the 1st term by the row U :, C is the range of variation of the real values of the argument x, 3) - the range of changes in the number of first members of the series, which must be taken into account when calculating. When calculating the functions "by recurrent formulas, the conditions mj" max t, t should be fulfilled. (3) Specific recurrent relations for calculating functions with regard to scales are given in Table. 5 ° The square brackets indicate the actions of the preparatory stage, which are used to calculate the value of the MF (X) (X) € (4) When performing the main stage of the operations, the actions associated with calculating the function C (|) and comparing the value of cd at the same time as others, the Analysis of the convergence of the series (Table 2) shows that to calculate the functions f (x) with a given error D in the practical range of and. changing argument X, it is necessary to calculate a limited number of first row members. This makes it possible to use the tabular method for calculating the function H () / g with the help of memory blocks (LF). When considering the functions Ч () (Table 3), it turns out that for various functions f (x) J the functions Ш () are described by the same formula. (e.g. sinx and shx; cosx and chx, arcsinx and arshxX. This allows you to use the same PDUs that store the lf (i) values to calculate various functions. The first PDU (BP-1) is used when calculating function e. In each cycle, the value of 1, which is the address of the cell, is applied to the input of the BP-1, and the output is taken to be the inverse of 1 / i. The number of the BP-1 cells is 14 (tabLo 2), and the width of each cell depends on the accuracy of the function H (i) and does not exceed the size necessary to represent the argument x. The second BP (BP-2) is used when calculating the functions sinx, cosx, shx, It consists of 28 cells (Table 2). In odd-numbered cells with addresses (2i-1), values of 1/2 {21 -1) are written, and in even-numbered cells with addresses 2i - values of 1/21 (21 + 1). The third power supply unit (.БП-3) is used for ... calculating the UI function: p. and contains 23 cells (table 2), in which - ii-t values are found. The fourth power unit (BP-D) is used in calculating the functions of arcsinx, arshx and (1 ± xG and contains 120 cells. The cells with even addresses contain the values (2i-1) / 2i, (2i4l) necessary to calculate the functions of arcsinx, arshx , and in the cells with Odd ", the addresses contain the values (2i-l) / 2i necessary for calculating the functions (1ixG. Thus, the total capacity of all PDUs that provide the calculation of 9 functions f (x) with an error of not more than 185 cells A necessary and sufficient condition for achieving the specified accuracy of the function f (x) is the fulfillment of the logical relation . Л, (., (Д) m-), (5) - -i / - I where and. Is the value of the j-ro bit in the binary representation of the value (Uy I, counted to the right of the comma. Thus, The device implements the following algorithm for computing elementary functions represented as Taylor series. In each computation cycle, the next member of the series is represented as a product of three factors: the value of the previous member of the series, a multiplier that is a function of the argument x, and a multiplier, which is the function of the number of a member of the row (1), and the multiplier that is a function of the argument x, for all members of the series has the same value and is calculated at the preparatory stage, and the multiplier, which is a function of the number of the member of the series, due to the limited number of calculated members of the series, is calculated by tabular method using persistent storage devices (Table . 3). When performing the main step of calculating the functions of the operation, which can be performed simultaneously with others, are combined in time (sampling of constants and the operation of the first multiplier 3, the second multiplier 4 and the adder 2). The device in accordance with the calculation algorithm works as follows. Initially, the registers 15 and 17 and the counter 14 are set to the zero state. When a request for calculating the function f (x) is received in block 1 of the control, the operation code is received for the operation register 15, the argument x is assigned to register 7, and the error register 17 is the value of the specified calculation error D. for example, for a binary fixed-number numeration system, the values are given considering the scale of the argument m, and the values of the calculation error taking into account the scale of the function II (Table 4). The operation code from register 15 is fed to the decoder 16, at the output of which a signal is generated for the operation being performed. 70710 coming to the control unit 1, the control unit 1 on the start signal starts to generate control signals in accordance with the timing diagram (Fig. 3). In this case, for each clock pulse from the output of the clock generator 22 clock pulses in the shift registers, the unit is shifted sequentially, which was first written to shift register 23 (FIG. 2). The shift registers 23 and 24 are intended for organizing the preparatory stage, and the shift register 25 for organizing the main stage of the function calculations. The operation of the device is synchronized by four series of sync pulses (CHIrCHi) shifted relative to each other. Consider the operation of the device on the example of calculating the functions sinx, cos X, arcs in x,. In 1i, shx, ch X, arsh x, (ItxHC Ha preparatory stage with the functions sin x. In xu arcsin X, sh x, arsh x in the register "e on one of the control signals generated by group 32 (Fig. 2) , the specified argument X is transferred from register 7, and a structural shift is made taking into account the scale of the function T. (Table 4) .When the functions (NXI) cos X, e, chx are entered, register 6 is entered into the register taking into account the scale of the function t. Thus, in register 6, the initial member of the row of WoStable 5 is formed. At selected scale factor values, group 32 generates P7-Pb control signals for arsh x ;; RB for 7.) -PJ - p6 for 1p IfL, arcs in x, e-j 2 for cb x; 2 P7 - RB for d-bx; RB for cos; RB for (1 ± x; - / FOR sinx; 2 The contents of register 6 are transferred to register 5) In addition, at the preparatory stage, the value of the pseudo-argument S (x) is calculated. The value of the pseudo-argument fCx can take the value or x (for functions (1 - x) e, or -X. (for (1 + xI, or x (for InjfTx arcsin x, sh x, ch x), or (for sin X, cos x, arsh x). If f (x) tx, This function is of the first type, if H (x) ± x, is of the second type. The operation type signals are formed by the OR elements 41 and 42. The output of the first shift register 23 when the functions of the first type are calculated using the AND element kk is connected to the input 3 second register 25 shift, ha, when calculating the functions of the second tp with the help of the element And A5 - to the input of the second shift register 2. To calculate the value of the pseudo-argument, the contents of register 7 are transferred to register 8 and the multiplier t is started. 7 of the pseudo-argument and is stored in it until the end of the calculations.When performing operations using the negative value of the pseudo-argument H (x), the inverse code value is output to the input of the multiplier 4. At the preparatory stage, when calculating the functions cos x, ch X, (1-t x), the summing counter is set to 1 by the signal from the output of group 31. When calculating other functions, the summing counter is initially set to O. Basic calculation step for all functions f (x) performed in the same way and built on the principle of deep combination of measures. In each cycle, the following actions are performed: a) sampling the next constant t) (l) according to the contents of summing counter 14; 2) multiplication by the multiplier C of the selected constant IP {i) by the pseudo-argument H (x); 3) multiplying, on multiplier 3, the contents of accumulating register 6 by the result of multiplying f (x). H (-f) obtained in the previous cycle; k) calculating the next approximate value of a function by summing the multiplication result obtained on multiplier 3 in the previous cycle with the contents of accumulating register 5:) U iU) -Uo-i-.lUH - «- Ur i-. . 5) comparison in block 18 of the multiplication result obtained in a given clock cycle on multiplier 3 with the contents of error register 17 and issuing a reset signal to control block 1 when a specified calculation accuracy is reached; 6) increasing the content of the summing counter T by one (when calculating FUNCTIONS. 5In X, cos X, arcs X, arsh x, sh x, h x, (H x), the contents of counter 1 y are doubled by 1). at the beginning of the main stage of the calculations, using the shift register 25, the control triggers 26-30 are sequentially set to 1. The unit states of the control triggers 26-30. allow the generation of the elements AND signals controlling the operation of the device according to the corresponding sync pulse (Fig. 2 and h). Moreover, group 33 generates the start-up signals of the ROM-1 (for the Start-up ROM-2 for sm x, .cos X, sh X and ch x), Start-up ROM-3 (for In li |), Start the ROM-4 (arcsin X, arsh x, (lixr). Group 35 generates signals to transfer the contents of register 7 to the input of multiplier 4 without changing () for functions with H (x) X and IP (x) x and with inversion (UM2) for functions with H (x) -X and H (x) -X. The control signals are generated periodically until the control triggers are reset 26-30. I The first calculation cycle of the functions € (x) is performed as follows: According to the contents of the counter 14 via the switch 13, depending on the control beep from the output of group 33, one of the following memory blocks 9–12 is accessed. As a result, the first constant of one of the following types 21-1 1 1 1 is extracted; 2I (2i4-T) 2i (2i - 1) 1. (21-1) 21-1 (Table 3). WyT 2i (2W) 2i-fr branded constant is taken to register 8 and multiplier 4 is started to calculate the product of the pseudo-argument C (x to constant C (-}). the product is transmitted to the input of the multiplier 3i at which it is multiplied by the contents of register 6. By this time, the contents of counter 14 change in accordance with the logic of operation, Keeping in Table. 6, either by 1 or 2. Through the commutation switch, the torus 13, one of the memory blocks 9-12 is accessed and the next constant is selected, which is received per register 8. On the multiplier 4, the next constant C is multiplied (/ { ) on the argument f (x. At this time, adder 2 summarizes the contents of register 5 with the multiplication result obtained on the multiplier 3. The result of the summation enters into the accumulating register 5. In addition, in block 18, the result obtained on the yMHO resident 3 is compared, with the contents of the register 17. Upon reaching a given When the conditions A are fulfilled, the block 19 outputs the process stop signal to the control block 1. The operation of the device in the following way is performed in the same way. /, page 5. Thus, the use of the device in general-purpose and specialized computers allows

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 | x) s4 functionality due to the implementation of these functions; save memory for storing corresponding standard subroutines and constants; to increase the productivity of the computer by reducing by 1, 0 times the calculation time of these functions; reduce the load of the arithmetic unit; to increase the productivity of a computer by eliminating the time spent on calling one or another standard subroutine from an external memory to an operational memory; increase the reliability of the computer and the reliability of the results of calculations both by saving memory for the subroutines and by improving performance. Table 1 k

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Claims (2)

1. Authors' certificate of the USSR ° 595738. kl. General P, 1978. 2. USSR authorization certificate ff / M t jft yfO & UfMt / jr i2LJ l ijlOM, fi / fOMO Z-Sfd tmeMfta. 19 Fah.g W Fjroifu fff / fiff I y, fftT ff y ifS MttyS f- "1 - r l ffjfff / ta l, / 4" i7o JffjfffiiyS