SU590750A1 - Device for effecting rapid fourier transformation - Google Patents

Description

The invention relates to the field of computer technology and can be used to solve problems of harmonic analysis, as well as in the numerical solution of partial differential equations on grid models, their devices.

A device is known for realizing a fast Fourier transform (FFT) 1 constructed using shift registers of various lengths.

The design of this device is complicated.

The closest to the invention to the technical essence and the achieved positive result is a device for realizing a fast Fourier transform 2, containing an information storage and conversion unit and a control unit, the first and second inputs and output of the storage and information converting unit the second output and the input of the coil unit.

The unit for storing and converting information in a known device is made in the form of addition and multiplication nodes on shift registers. Due to the fact that such a device is based on the principle of sequential processing of information, its disadvantage is that it has a relatively low computation speed and is also rather weak STABILITY

relatively small initial perturbations. The increase in speed in the known device can be achieved due to the use of parallel sections, which leads to significant structural complications and increase the cost of the device. In addition, the digital information processing method does not allow using the known device directly as processors for grid modeling devices when solving partial differential equations, thus reducing the functionality of the device.

The goal of the acquisition is to increase speed.

The goal is achieved by the third and fourth outputs of the control unit connected to the third and fourth inputs of the information storage and conversion unit, and the information storage and conversion unit contains an input memory node, an output memory node, the first and second analog Fourier transform nodes, and The first and second outputs of the output memory node are connected to the first inputs of the first and second analog Fourier transform nodes, the second inputs of which are connected to the second input of the block, the first and second The inputs of the output light node are connected respectively to the first input of the block and the input of the device whose output is connected to the output of the output memory node; the first outputs of the first and second analog Fourier transform nodes are connected respectively to the first and second inputs of the input memory node, the third and fourth the inputs of which are connected respectively to the third and fourth inputs of the block, and the output of the block is connected to the second outputs of the first and second analog Fourier transform nodes.

The goal is achieved by the fact that the control unit contains an arithmetic logic unit, a cycle counter, a step counter, an AND element, a switch and a digital-to-analog converter, the first and second outputs of the arithmetic logic node being connected to the input of the switch and the digital-analog converter, respectively whose outputs are connected respectively to the first and second outputs of the block, the first, second, third outputs of the cycle counter are connected respectively to the third output of the block, with the first input arithmetic About the node and the first input of the element I, the first, second, third outputs of the step counter are connected respectively to the fourth output of the block, to the second input of the arithmetic logic node and to the input of the cycle counter, the second input to the output of the And element are connected respectively to the input of the block and the input step counter.

The drawing shows the block diagram of the device.

The device for implementing fast Fourier transform contains information storage and conversion unit 1 with inputs 2-5, input 6, which is the device input, output 7, is the device output us, output 8, and control unit 9 with input 10 and outputs Irychem, the storage and transformation unit consists of an input memory node 15 with inputs, an output memory node 20 with inputs 21-23 and outputs 24-26, a first node 27 of an analog Fourier converter with inputs 28, 29 and outputs 30, 3: 1, the second node 32 of the analog Fourier transducer with in Odes 33, 34 and outputs 35, 36, and the control unit contains arithmetic logic unit 37 with inputs 38, 39 and outputs 40, 41, switch 42, digital-to-analog converter 43, loop counter 44 with input 45 and outputs, counter 49 steps with input 50 and output, the element And 54 with inputs 55, 56 and output 57.

The device works as follows.

Before the start of transformation, in block 9 of the control, the size of the information to be converted is set (power of 2), through input 6 of the device to the inlet 22 of node 20, the original information is recorded with a memory output.

By the signal "start of operation, information on the current step and fast Fourier transform cycle from counters 44 and 49 is given

to node 37, where the numbers of the two cells of the node 20 of the output and them are needed at this transformation step, as well as the arguments of trigonometric functions in accordance with the Fourier fast transformation algorithm. Information about the cell numbers from the output 40 of the node 37 through the switch 42 is fed to the input 21 of the node 20, resulting in the contents of the calling cells through the outputs

24, 25 knots. 20 is supplied to the first input 28 of the node 27 and to the input 33 of the node 32, to the inputs 29, 34 respectively of the nodes 27 and 32, through the digital-to-analog converter 43 the arguments of trigonometric functions are received. WITH

outputs 30, 35 of information nodes 27, 32, and transformed in accordance with the fast Fourier transform algorithm, are recorded at inputs 16, 17 of the first cells of the registers of node 15 of the input memory.

From the outputs 31, 36 of the nodes 27, 32 from the output 8 of the block / to the input 10 of the block 9, a feedback signal is fed, which from the input 55 of the element I 54 is fed to, the counter 49, increasing its contents by one. Exit 51

the counter 7 through the output 14 of the block 9 and the input 5 of the block / to the node 15 receives a signal, as a result of which the second cells of its registers are connected to the inputs 16, 17 of the node 15 (i.e., the register registers are shifted).

A new fast Fourier transform begins.

In the event of overflow of the counter 49, signifying the end of the next fast Fourier transform cycle, a reset occurs.

counter 49, and the signal from the output 52 of this counter goes to the input 45 of counter 44, increasing its content by the unit. At the same time, from its output 46 through output 12 of block 9 to input 4 of block 1 and to input 18 of the node

15, a rewrite signal is given, as a result of which information from the registers of the node 15 of the input and these types is not recorded at the input 23 of the node 20 into the output memory. A new fast Fourier transform cycle begins.

When the counter 44 overflows, meaning the end of the fast Fourier transform, the counter 44 is reset, and the overflow signal from its output 48 enters the input 5S of the And 54 element, with the result that

the feedback loop is broken. Information is output from the device.

In connection with the fact that data processing is carried out in parallel in this device, the computational rate increases significantly. In this case, a significant increase in speed will occur at the stage of calculating trigonometric functions. The total calculation time in each case is determined by the specifics of the task and

decreases on average by several times compared to using a digital computer. Since the crucial elements of the device are analog action, the computational process will always be stable with respect to small

disturbances. In addition, the proposed device can be used directly (without auxiliary elements) as an attachment to counting simulators for the numerical solution of partial differential equations.

Claims (2)

Invention Formula A device for realizing a fast Fourier transform comprising an information storage and conversion unit and a control unit, wherein the first, second inputs and output of the information storage and conversion unit are connected respectively to the first, second outputs and the input of the control unit, characterized in that in order to increase speed The third and fourth outputs of the control unit are connected to the third and fourth inputs of the information storage and conversion unit, and the information storage and conversion unit contains an input input node AM, output memory node, first and second analog Fourier transform nodes, the first and second outputs of the output memory node are connected to the first inputs of the first and second analog Fourier transform nodes, the second inputs of which are connected to the second input of the block, first and second the inputs of the output memory node are connected respectively to the pen in the input of the block and the input of the device, the output of which is connected to the output of the output memory node, the first outputs of the first and second analog Fourier transform nodes are connected to tvetstvenno with first and second inputs of the input node memory, third and fourth inputs which are respectively connected to third and fourth inputs of the block and the output block connected to the second outputs of the first and second analog Fourier transform nodes. 2. A device according to claim 1, characterized in that the control unit contains an arithmetic logic node, a cycle counter, a counter counter, an element AND, a switch and a digital-analog converter, the first and second outputs of the arithmetic logic node being connected respectively to the input of the switch and the input of the digital-analog converter, the outputs of which are connected respectively to the first and second outputs of the block, the first, second, third outputs of the cycle counter are connected respectively to the third output of the block, to the first input of the arithmeticological and the first input of the element And, the first, second, third outputs of the counter of the joints are connected respectively to the fourth output of the block, to the second input of the arithmetic logic unit and to the input of the loop counter, the second input and output of the element And are connected respectively to the input of the block and the input step counter. Sources of information taken into account in the examination: 1. US patent number 37883258, class. 340-172. 5, 1974. 2. Authorship certificate USSR № 382091, cl. G 06 F 15/34, 1971.