SU577686A1 - Reversible five-digit binary-decimal counting decade - Google Patents

Claims (2)

: 54) REVERSIVE FIVE-DISCHARGE BINARY-DECIMAL ACCOUNT DECADE The drawing shows the structural electrical circuit of the described counting decade. The decade contains D-flip-flops 1-5, logic elements 2I-2ILI-1E 6-10 output logic element 2I-2ILI- -NE 11, addition control bus 12, subtraction control bus 13, counting pulse bus 14 and bus 15 setting zero pulses The output signal is removed from the output. The principle of operation of the counting decade is as follows: In the initial state, the decade is set to 00000. When rasterized in the code of the driving potential on the bus 12 D-trI1, the first discharge bit is ready to record information by high potential from the output of the logic element 2I-2IL. NRA 6. High potential At the output of this element, the interface is encased by a connection from the output of the D-flip-flop 5. At the inputs of the D-flip-flops of the remaining bits there is a low potential that prohibits the writing of the unit. When the counting pulses arrive for no more than 14 decades, starting from the initial code 00000, it successively assumes five states 1 0000.11000 11100, 11110, 41111. the counting pulse provides the inverse overwriting of information in the first bit and confirms the unit states of the remaining bits of the decade — code 01111. The further score will be characterized by the sequence of codes 00111 00011, 00001, 00000. Thus, the decade has ten stable states and under the action of counting pulses successively moves from one state to another, ensuring the counting of pulses by Recording the unit to the next modulating reversible binary-ten decade is carried out from the output of the output logic element 2I-2OR-NOT 11 overvoltage potential at the output of D-flip-flop 5 at the tenth counted nominal impulse. In the subtraction mode with a resolution potential on bus 13 and the initial UOOOO state — code — to record information with high potential from the output of logic element 2I-2 OR-NOT 10 D-flip-flop 5 is ready. High potential at the output of logic element 2I-2 OR-NOT 10 formed by feedback from the output of the D-flip-flop 1. Upon receipt of the counting pulses, the writing of the unit occurs in the reverse order, starting with the D-flip-flop 5. The decade successively takes on the states characterized by codes that are inverse to the direct counting codes. The unit is borrowed in the next reversible binary-decimal decade from the output of the output logic element 2I-2ILI-NOT 11 by the potential drop at the output of the D-flip-flop 1 when the tenth pulse arrives at the counting input. The positive feature of the reverse binary decimal decade is the high speed and ease of decoding the states. The speed is determined by the time it takes to set one bit,, 10 01 t SPT ..- 2 11,, j respectively. Invention Form Reversal ptyra of the bottom of a binary-decimal counting decade, containing an output logic element 2I-2ILI-NOT and in each bit D-flip-flop and a logic element 2I-2ILI-NOT, the output of which is connected to the D-input of D-flip-flop, the other two inputs of which are connected to the zero and counting impulse buses, and the two inputs of each of the logic elements 2I-2, OR-NOT are connected to the addition and subtraction control buses, characterized in that, in order to increase speed, the third input of the logic element 2I- 2OR — NOT every bit but n The first is connected to the first output of the previous D-flip-flop, the fourth input of the 2I-2ILI-NOT logic element of each bit, except for the first one, to the first output of the subsequent discharge of the D-flip-flop, and the third input of the 2I-2OR-NO logical element the first bit - with the second output of the Drigger of the same bit and the third input of the output logic element 2I-2ILI-NOT, the fourth input of which is connected to the fourth input of the logic element 2I-2ILI-NO nogoOn discharge and the second output of the D-trigger of the first bit Yes. Sources of information taken into account in the examination: 1. USSR author's certificate No. 414745, cl. H 03 K 23 / 00,17.06.72. 2. The UK patent M1264181, class, Q 4 A, 16.02.72,