SU548859A1 - Multi-channel priority interrupt device with automatic generation of a priority application code - Google Patents

Description

it is connected to the second input of the subsequent channel, the second group of inputs of each channel, except the last one, is connected to the fourth outputs of the subsequent channels, and each channel, except the last, additionally contains a switch and an OR element, and the second group of channel inputs through the OR element is connected to the first the switch input, the second and third inputs, the first and second outputs of which are connected respectively to the third and fourth outputs, to the upstream input of the first-order block and to the third output of the channel, and the second input of the first channel union of the corresponding output of the control unit.

The block diagram of the device shown in the drawing.

The multichannel priority interrupt device with automatic generation of the priority application code contains the first channel 1, the second channel 2, the last channel 3, the control unit 4, the encoder 5, the register 6, the OR element 7, and each channel contains the priority block 8, the switch 9, the element OR 10, a group of inputs 11, input 12, outputs, outputs 17, 18 of the sequence block, output 19 of the element OR.

The drawing indicates: 20 - device output; 21, 22, respectively, the group of outputs and the output of the control unit, 23, the enabling output of the control unit, 24, 25, respectively, the control and information inputs of the register.

The device works as follows.

The request signals arriving at the input groups M of channels 1-3 are divided into priority levels in such a way that the group of inputs 11 of channel 1 corresponds to the programs of highest priority, and the group of inputs 11 of channel 3 to lower-priority programs. All programs implemented on the basis of requests from a particular group have one priority and are launched in the order in which requests are received.

To bring the device into a working state, before starting operation, the control unit 4 sends signals to the initial state of the output group 2il, which initialize the blocks of priority 8 of each of the channels 1-3. Requests for the implementation of programs come in groups of inputs AND channels 1-3 to the corresponding blocks of order 8, where they are queued in the order of their arrival. After recording any request to one of the blocks of order 8 at the output 14 of the channel, the signal arriving through the OR element 7 to the input of the control unit 4. From the output 22 of the control unit 4 to the input 12 of channel 1 a trigger signal is received.

If there is a signal at one of the inputs of the group of inputs 11 of channel 1, the switch 9 of channel 1 generates triggering signals at the outputs 16, 13. The signal at the output 16 arriving at priority 8 is generated if any of the following conditions is met: a request is written at block 8 channel 1 (there is a signal at the output of block 17) and queues in each of the blocks of 8 channels 2, 3, are not equal to the maximum (no signal at output 19 of the element OR 10 of channel 1); the queue in block 8 of channel 1 is maximum (there are signals at the outputs 17, 18 of this block) for any values of the queues in blocks of 8 channels 2, 3. And the appearance of a signal at the output 16 of the switch 9 of channel 1 starts the block 8 of channel 1, as a result which, from output 15 of block 8 of channel 1, removes the signal that arrives at that input of the encoder 5, which corresponds to the type of request received for service. The information input 25 of register 6 enters the code of the initial address, which, by a signal applied to control input 24, arrives at the output 20 of the device.

The signal at output 13 of channel 1, which arrives at the start of a block in channel 2, is generated when at least one of the following conditions is met: the highest priority queue is zero (no signal at the il8 output) for any values of the queues of lower priority levels; the highest priority queue is not zero, but is not maximum (there is a signal at output 18 with no signal at output 17) and the queue in one or several blocks of the next 8 subsequent channels is maximum (there is a signal at output 19 of the element OR 10 of channel 1).

In these cases, the signal from the output 13 of the switch 9 dripped 1 is fed to the input 12 of channel 2 of the switch 9 of channel 2, which similarly produces signals at output 16 or 13. As a result, the choice is made to service the request recorded in block 8 of channel 2 or transition to launch blocks of 8 subsequent channels. Such an algorithm

the operation of the switch 9 provides the discipline for program startup described above, which significantly reduces the likelihood of losing requests for lower priorities and reduces the amount of equipment needed to fix them.

Claims (2)

1.Avt. St. No. 468240, cl. G 06F 9/18, 1972. 2. Avt. St. No. 206891, cl. G 06f 9/18, 1966 (prototype). 22