SU489102A1 - Binary code converter - Google Patents

Description

one

This invention relates to automation and computing.

A known converter of a binary code into a binary-decimal code of degrees and minutes, comprising a pulse generator,

binary decimal degrees and minutes, a binary counter, three decoders, a gate, a division into three divisions, an OR circuit, and a delay line.

However, this device allows

implement only the direct conversion of the BINARY code to the binary-decimal code of degrees and minutes.

The purpose of the invention is to expand the field of application of the device by providing both a direct conversion of a binary code into a binary-decimal code of degrees and minutes, and a reverse conversion of a binary-decimal code of degrees and minutes into a binary code.

This is achieved by the fact that the device contains a fourth decoder, the inputs of which are connected to the outputs of the binary-decimal counters of degrees and minutes, the encoder, the outputs of which are connected to the input

The higher bits of the binary counter, the second OR circuit, the first input of which is connected to the output of the first decoder, the remaining inputs are connected to the outputs of the fourth decoder and inputs of the encoder, and the output to the input of the valve, and the control panel connected to the inputs of the first and second decoders and through the scheme NOT - to the input of the fourth decoder.

Diagram of the device shown in the drawing.

The device contains a pulse generator 1, a gate H, a binary counter 3, a binary-decimal counter of degrees 4, a binary-decimal counter of minutes 5, a circuit of 6 divisions into three, a decoder 7 that decrypts the binary state of the counter, a decoder 8, deciphering states of the most senior bits of the 9 two-stage counter, in which transfer spins are excluded; a decoder 10 serving to extract correction pulses, a delay line 11, an OR circuit 12, an additional low-order bit 13 of a binary note, input buses 14, an output pin 13,

a decoder 16 deciphering the states of counters of degrees and minutes, multiples of 45 °; encoder 17 used to generate a three-bit binary code that is intended for writing to a high-order 9 binary counter in the inverse transform j second OR circuit 18, the first input of which is connected to the binary counter zero state decoder, the rest of the inputs to the decoder outputs 16, and the output is connected to the control input of the valve 2, the busbar control 19 connected to the inputs of the decoder 7 and 8 and through the circuit HE 2O to the input of the decoder 16; bus 21 write binary decimal code, the output bus 22 binary code.

The device works as follows

i When a signal is fed to control bus 19, output (direct conversion of a binary angle code into a binary decimal code of degrees and minutes), a decoder 7 of the zero state of the binary counter and a decoder 8 high bits of the binary counter are turned on, and the decoder 16 is turned off. In this case, the operation of the proposed converter is identical to the work of the known converter.

 When a signal is applied to the control bus 19, the input (conversion of the binary-decimal code of the degrees and minutes to the binary code) is decrypted in grades 7 and 8, and the decoder 16 is turned on.

The pulse sequence produced by generator 1 does not pass through valve 2 until the binary-decimal counters of degrees 4 and minutes 5 are in the zero state. After writing to the binary digits counters by

 To the tires 21 of the number to be transformed, the deflector 16 issues through the scheme OR 18 to

gate 2 is the enable signal. The valve opens, and a sequence of pulses is simultaneously applied to the OR 12 circuit and to the dividing circuit 6. From the output of the circuit OR 12, the sequence of pulses goes to the additional least significant bit 13 of binary counter 3, working on the subtraction. The first, a pulse arriving at the input of binary counter 3, sets all its bits except the three oldest ones, to state 1, and the subsequent H. Mnyjif;, cbi produced a subtraction from this code.

From the output of circuit 6, the divisions into three pulses arrive at the input of the minute counter 5. When the code recorded in the counters of degrees 4 and minutes 5j becomes a multiple of 45 °, the decoder 16, through the circuit OR 18, outputs a inhibitory signal to the valve 2: which will stop the pulse on double counter 3 and on the input of the circuit 6; not three. At the same time, the decoder 16 sends a signal to the encoder 17, which generates a three-digit binary code corresponding to 0 (45 ° C, where (X is the value of the angle contained in the binary-decimal counters of degrees 4 and minutes 5 at the moment the signal is issued behind the preta decoder 16. The three-bit binary code from the output of the writer 17 is fed to the inputs of the three most significant bits of the 9 binary counter.

The correction circuit, consisting of the decoder 10 and the delay line 11, works in the same way as in the direct conversion.

Thus, after stopping the supply of pulses to the input of a binary-decimal counter 5 minutes and to the input of binary counter 3, the binary code of the angle will be fixed in the latter.

Before each new conversion, binary counter 3, binary decimal counters 4 and 5, and circuit 6 of dividing into three | set to zero.

Subject invention

Converter binary code auth. St. L / g 346719, characterized in that, in order to expand the field of application, the device contains a fourth deshi ({rator, the inputs of which are connected to the inputs of binary decimal degrees and minutes, an encoder, the outputs of which are connected to the inputs of the higher bits of the binary counter , the second OR circuit, the first input of which is connected to the output I of the first descrambler, the remaining inputs are connected to the outputs of the fourth decoder and the encoder inputs, and the output is connected to the input of the valve, and the control bus connected to the inputs of the first and second decoder and through the scheme NOT - to the input of the fourth decoder.

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