SU451201A1 - Single-ended impulse distributor on an annular shift counter - Google Patents

Description

one

The invention relates to computing, automation and telemechanics.

Known single-ended pulse distributors on 1 altsevyh counters. Known devices at each time {t de contain a trigger and two AND-NOT schemes. A single trigger output is connected to the input of the first NAND circuit, whose inputs are also connected to the clock bus and the output of the first NAND circuit of the previous one.

, the discharge, and the output - with the output of the device, the input of the first NAND circuit, and the unit

the trigger input of the next bit and the input of the second NAND circuit of the same bit, the other input of which is connected to the single trigger output of the next bit, and the output to the zero trigger input of the same bit. The reset bus is connected to a single input of the first trigger and zero inputs of the following trigger bits.

However, the known distributor is characterized by an uneconomical number of circuits per channel.

The aim of the invention is to simplify the distributor.

For this purpose, the zero output of each digit of the discharge is connected to the zero input 5 of the previous discharge trigger, and the output of the NAND circuit of each discharge is connected to the single input of the previous discharge trigger.

The drawing shows the block diagram of the limiter.

The one-shot pulse distributor contains an RS-trigger on each AND-HE 1 and AND-NO 2 circuits, with the AND-HE 1 scheme being the unit arm of the trigger, J and the AND-HE 2 scheme being zero, the AND-3 scheme ; the output of which is connected to the output 4 of the yciv device, the input AND-NOT 1 of the same time. input AND-NO 3 of the next bit and input AND-NO 1 of the previous bit, and 0 input - with the clock pulse bus 5, outputs of the AND-NO circuit 1 and AND-NO 3 of the previous bit; the reset bus 6 is connected to the input of the last bit AND-NOT 1 circuit and the inputs of the AND-NOT 2 circuits of the remaining 5 bits, the input of the AND-H | 2 2 circuit

bit is connected to the output of the circuit NAND

2 next bit

l-distribution works as follows.

Before starting work on reset chic 6, a negative impulse is given, which flips all the triggers to the zero position, and the trigger of the last discharge to the single position. At the same time, the first-stage IS-HE 3 circuit is prepared to operate. When the clock pulse arrives, the first-stage IE-HE circuit 3 will trigger and re-trigger the first one.

; discharge in a single state. At this time, the output of the first-stage AND-NOT 2 circuit tends to transfer the trigger of the previous discharge to the zero state, but its operation delays the low potential from the output of the AND-3 circuit of the first discharge. With the OKOH airaeM clock pulse, a high potential is set at the output of the NAND 3 circuit, and the trigger of the previous bit goes into the zero state. Thus, the distributor will be under. prepared for issuing a pulse at the output 4 of the second discharge and its further operation is similar to that described.

Subject of invention i

Single-ended. pulse distributor

on an annular shift counter, each trigger contains a trigger on two NAND schemes and an NAND scheme, the output of which is connected to the device output, with a single trigger input of the same bit and the next stage NAND input, and inputs - with a clock pulse width, single trigger output and output

AND-NES of the previous bit, a single output of the trigger of each bit is connected to the input of the IS-N scheme of the next bit, zero input of the trigger of each bit is connected to the reset width with which

A single trigger trigger input is also connected, characterized in that, in order to simplify the distribution, the zero trigger output of each bit is connected to the zero trigger input.

previous bit, and the output of the circuit is NOT

each bit is connected to a single input. previous trigger house.

/;