SU447754A1 - Memory device - Google Patents

Description

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The present invention relates to the field of storage devices.

A memory device is known which contains information registers, an input register connected to the control and.

Uniforms 1 Ashnam, OR Schemes and the Arrangement Block.

When storing transit information in this device, a number of registers is necessary, twice the number of words simultaneously in the device. In addition, it is possible asynchronous when rewriting information from the register to the register (TO requires special schemes and complicates the design, and the rewriting of words from the register to the register consumes additional energy. The described device differs from the well-known in that it contains , cxBNt And according to the number of chipformed registrars, rev, controlling inputs of which are connected to the corresponding outputs of the distribution block, information inputs to the output of the input register, and outputs to information outputs isters, exits |

which are connected to the inputs of one of the OR circuits. The control input of each circuit group AND, except the last one, is connected to the control input of the subsequent information register, the control input of the last group of AND circuits is connected to the control input of the first information register and one of the inputs of another OR circuit, the output of which is connected to the distribution input block.

These differences allow us to simplify the device, reduce the power consumed by it and increase its reliability.

The drawing shows a block diagram of a storage device.

The device contains an input register 1, a trigger 2, a differentiating circuit 3, an OR circuit 4, the output 5 of which is connected to the distribution unit 6, a group of circuits AND 7, information registers 8, the outputs of which are connected to the inputs of the circuit OR 9.

I Input register 1 is connected to control 10 and information 11 buses.

The control inputs 12 of the circuit groups And 7 are connected, to the corresponding outputs of block 6, the information inputs 13 to the output of register 1, input 12 of each group And 7 of the circuits, except the last (right-hand drawing), is connected to the control input 14 of the subsequent register 8, input 12 of the last group of circuits AND 7 is connected to the control input 14 of the first register 8

(left-in the drawing) and input 15 of the circuit

OR 4.

Distribution block 6 contains electronic relays 16 ,, whose outputs are connected to one input of the circuits And 17, the other inputs of which are connected to the control bus 1O, and the outputs to the inputs of block 6.

The output of each circuit And 17, except the last one, is connected to the input of the subsequent pe.ie 16.

The device works as follows

Post control signals to the 1O bus and one inputs of the And 17 circuits, code slots - to the voltage 11 during the pause between the control pulses. The first control pulse records 2 units in trg1 ggera. The signal from its output goes to the d junction of jly 3, with which the negative pulse, which is equal to

To the front of the pulse, through the OR 4 circuit, it is fed to the input of the first relay 16 and starts it. From the B1.1 input of the relay 16, a pulse with a duration equal to the follow-up period of impulse 1: control is fed to the other; the first input of the first circuit. 17. The control signal passes through the circuit AND .L7 and is fed to the input 12 of the first group of circuits AND 7, through which the code word read from the input register 1 is written to the first register 8. At the same time, the control pulse from the output of the first circuit 17 is fed to the input 14 of the second register 8, from which the code word (with {

| its presence) through the scheme OR 9 enters the output device. From the output of the first circuit AND 17, the control module will also go to the input of the second relay 16 and start it. A pulse from the output of the second relay 16 is fed to one of the inputs of the second circuit AND 17, preparing it to pass the next control pulse. The second control pulse reads the next word from input register 1, passes through the second circuit 17, allows writing this word to the second register 8, reads the information from the third register 8 through the second group of circuits And 7, and starts the third relay 16, preparing the seam conditions for writing the next word to the next information register 8 and t, d.

Formula of invention

A storage device containing information registers, an input register connected to the control and information shells, an OR circuit and a distribution unit, characterized in that, in order to simplify the device and increase its reliability, it contains groups of AND circuits and by the number of information registers that control e inputs of which are connected to the corresponding inputs of the distribution block, information inputs to the output of the input register, and BF and inputs to the inputs of information registers, the outputs of which are connected to the inputs of one of the OR circuits, the control input of each group of AND circuits, except the last one, is connected to the control input of the subsequent information register, the control input of the last group of AND circuits is connected to the counteractive input of the first information register AND one of the inputs of another OR circuit, the output of which connected to the input of the distribution unit

I.

JO Oh

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