SU432496A1 - PARALLEL CUMPER OF TYPE WITH ACROSS TRANSFER - Google Patents

Description

one

The invention relates to the field of computing, namely accumulators of its type.

Known to accumulate | Ie adders with end-to-end transfer.

A disadvantage of the known parallel accumulators of the transfer type is the difficulty of making the transfer chain formation circuits. In the well-known parallel accumulator of the end-to-end transfer type, the end-to-end transfer signal generation circuit includes a transfer valve B, a forward cyclic transfer valve B-1, a delay line or a trigger that fixes the transfer signal.

In order to simplify the circuit of the formation of the signal of the end-to-end transfer in each bit, the unit and zero outputs of the summing trigger are connected respectively to the "counting input and the input" setting 1 transfer signal memory trigger, the zero and unit outputs of which are connected respectively to the next first bit of the inputs “Control of 1 trigger of the memory of the transfer signal and the valve (valve) of the transfer signal, the output of the latter is connected through the valve of the input of the number to the counting input of the summing trigger.

Functional diagram of one of the bits

binary parallel adder with end-to-end transfer shown in the drawing.

Each bit of the adder contains a summing trigger 1, a memory trigger for the transfer signal 2, an input valve for the summand numbers 3, and a transfer input valve 4 for the logical elements of the AND –NE for high potentials. The single and zero outputs of summing flip-flop 1 are connected respectively to the input "counting start and input" setting 1 flip-flop of the signal of the transfer 2 of the same bit. Zero and single outputs of memory transfer trigger 2 are connected respectively to

Next, the first bit to the input “control 1 of the memory trigger of the transfer signal 2 and the input signal of the transfer signal 4. The output of the transfer valve 4 through the input valve of the numbers 3 is connected to the“ counting input of the summing trigger 1. The summing trigger 1 can be performed on any the counting start circuit, the memory trigger of the transfer signal 2 must have the inputs: "count start," control 1, "set 1," control O, "set O. The counting start occurs at the time of the negative edge of the potential change at the" count input at high tents on all other entrances. Setting the trigger to a single (zero) state is either low

the input potential “installation I (“ installation O) ”is a low potential at the“ counting input and high potentials at the remaining inputs, or low potentials at the inputs “installation 1 and“ control 1 (“installation O and“ control O) at high potentials at the remaining entrances. When using the same trigger as a summer, all of the listed control possibilities ("Set 1," Set O) can be used to control the adder.

In the proposed adder, the addition of binary numbers is carried out in two stages.

1. First, summing triggers 1 produce a one-by-one addition of the number stored in them and the number entered through the number entry valve 3. The result of one-bit addition (one-bit amount) is stored on the summing triggers 1, and at the same time memory triggers These transfer signals 2 generate transfer signals, including the end-to-end transfer signal, if this is dictated by the addition conditions.

2. Then, according to the command "transfer, after forming the end-to-end transfer signal to the valve of the input of transfer signal 4, in accordance with the transfer signals from the previous low-order bits, in all bits, the summation on the summing triggers 1 transfers with the same sum is performed. At the outputs of the flip-flops 1, signals are generated representing the final result of the addition of two numbers (final sum), which can be stored in the adder until the next addition.

If it is required to add another number to the stored amount, then after the "transfer" command it is necessary to set the memory triggers of the transfer signal 2 to the zero state (Transfer Extinguishing), supplying low potential to the transfer extinguishing inputs. To reduce the cycle time of adding numbers, the transfer cancellation in this adder can be performed simultaneously with the input of the term number. If it is required to extinguish the number in the adder, then it is sufficient to apply simultaneously to the inputs “setting O of summing triggers 1 of all bits a low potential. At the same time, the trigger signals of the signal of the transfer 2 should also be set to the zero state.

When the adder arrives at the inputs of the addendum, the number of low-potential pulses representing the addend numbers, in those bits where the digit is equal to one, high-potential impulses are generated at the outputs of the input valves of 3. These pulses arrive at the “counting input of summing triggers 1 and prepare them for counting triggering. The counting start is carried out during the formation of the trailing edge of the pulses, which represent the summands of the numbers, when a negative front is formed at the counting inputs of the I trigger. Triggers 1 are non-switched to the opposite state of the initial state, thereby performing a random addition of numbers. Depending on the bit size of this bit and the previous low bits, the signal to transfer to the next most significant bit is generated in two ways.

a) If a unit is stored in this bit, then at the unit output of flip-flop 1

there is a high nottial, which prepares the trigger 2 for the counting start, and if in this bit another unit is entered during the input of the term number, the transfer signal is generated in the switching element

the summing trigger 1 from the single state to the zero state, when a negative potential difference is formed at its single output, which triggers the trigger 2 to the single state. At the outputs of trigger 2, signals appear that reflect the transfer to the next most significant bit.

b) If a unit (zero) is stored in this bit and a zero (one) is entered into this bit during the input of the bit, and the transfer signal in the inverse code is received from the previous minor digit, the trigger control 2 is triggered, then trigger 2 also switches to a single state, generating a pass-through transfer signal to the next

older bit

The cause of the trigger 2 in this case is the supply of a low potential at the same time pa inputs "control b and" set 1.

After forming the end-to-end transfer signal, high potentials are set on the transfer entry valves 4, which reflect the transfer in the forward code. Upon receipt of the signal “transfer of valves 4, to the second inputs of which, at this time, the transfer signal arrives from the previous low-order bits, the low potential pulses are transmitted to the second inputs”. As a result of their impact on the input valves of numbers 3 at the outlets

These valves produce high potential impulses that prepare the triggers 1 for counting start. Counting starts occurs during the formation of a negative pulse front of the command "rewrite, when

the counting inputs of the triggers 1 also form a negative front. Triggers 1 are switched to the states corresponding to the final sum and memorize it. After the final sum has been generated, the memory triggers of the transfer signal 2 are returned to the initial zero state by a low potential pulse (" transfer quench) received at the " setting O of these triggers. When a pulse arrives

“Transfer cancellation, regardless of the potential value at the remaining inputs, at the zero output of flip-flop 2, a high potential arises, which goes to the input“ control 1 flip-flop 2 of the next higher bit and breaks the through-through signal circuit