SU429537A1 - MULTI-STABLE ELEMENT WITH 2 / V + 1 SUSTAINABLE STATES - Google Patents

Description

one

The invention relates to the construction of computer units and discrete automation in microelectronic performance, in particular in the form of large integrated circuits.

The well-known multistable element with 2.Vjl stable states (where, 2, 3 ...) is built in the logical AND-OR-NOT basis based on one memory trigger, having 27V- | -1 stable states, and one switching trigger device that synchronizes the switching of the trigger.

The purpose of the invention is to simplify the design of a multi-stable element and reduce its power consumption.

For this, a multi-stable element with steady states (where, 2, 3, ...) is built on the basis of connecting one memory trigger with 2: V + 1 steady states and one switching trigger device that recalculates 2N input pulses from module 2, registration of the 2L pulse and reset to the initial state. at the back of the () pulse, and recalculates the input pulses modulo 2 / V -) - l in code "1 from (2.V + 1) .

On fkg. one . a functional scheme of the proposed multi-stable element with 2L -} - 1 stable states is presented; in fig. 2 - state table of this element.

A multistable element with 2LG + 1 stable states (where, 2, 3 ...) is built on a logical basis AND-OR-NOT and is formed by connecting a memory trigger with

stable states (1-4 ... 5-7) and switching trigger device 8-10, recalculating 2N input pulses modulo 2, registering a 2N pulse and resetting to the initial state by the falling edge of the () -th pulse.

The memory trigger arms each contain one information input valve 11-17 and one memory valve 18-24 to form trigger connections: the memory valve inputs of any memory trigger arm are connected to the outputs of all other arms of this trigger. Information (counting) input of a multi-stable element with 2Л- | -1 stable

The states are connected to the first inputs of the information entry gates of all the arms of the memory trigger and to the inputs of the memory gates 25 to 28 of the switching trigger device. The second inputs of the information entry gates are all

the odd (except the last) memory trigger arms are connected to the output of the zero arm 8 of the switching trigger device, and the second inputs of the information input valves of all the even memory trigger arms are connected to the output of the unit arm 9 of this trigger device. The second input of the two-input information input valve of the last arm of the memory trigger is connected to the 2L switching arm of the switching device. The remaining inputs of the information entry gates of all odd (except the last) memory trigger arms are connected to the outputs of all the other arms of this trigger, with the exception of the outputs of the previous adjacent shoulder, including the last for the first and next to last shoulder; the remaining inputs of the information input gates of all the even arms of the memory trigger are connected to the outputs of all the other arms of this trigger, with the exception of the outputs of the previous adjacent arm and the last arm. The zero shoulder 8 of the switching trigger device contains: unit input valve 29, the first input of which is connected to the output of the unit arm 9 of this trigger device, and the remaining inputs to the outputs of all even memory trigger arms except its penultimate shoulder; gate 30 of input of the number 2jV, the first input of which is connected to the output 2.V-of the switching device trigger arm, and the second input - with the output of the last memory trigger lever; two memory gates 25 and 26, the second inputs of which are connected respectively to the outputs of the 2N-ro and the unit arms of the switching trigger device. The unit arm 9 of the switching trigger device contains: an input zero input 31, the first input of which is connected to the output of the zero arm 8 of this trigger device, and the remaining inputs from the output 35 of all odd memory trigger arms except its last shoulder; valve 32 input number 2N, the input of which is connected to the output 2N-ro arm 10 of the switching trigger device; a memory valve 27, whose input co-40 is single with the output of the zero arm 8 of this trigger device. The 2jV-Hoe arm 10 of a switching trigger device comprises: an input zero gate 33, the input of which is connected to the output 45 of the zero arm of a switching trigger device; the input gate 34 of the unit, the first input of which is connected to the output of a single arm of this trigger device, and the second input - with the output of a 2M arm of a trigger 50 memory, and the memory gate 28, the second input of which is connected to the output of a single switching arm trigger device. The principle of operation of the multi-stable element is 55 ta with 2iV + l stable states (where., 2, 3 ...) is that when Leninin input pulses are received, one arm of the memory trigger will switch, the choice of which determines only the mi previous-60 stitch (. or the last - for the first) shoulder of this trigger and switching trigger device. In this case, the pulses from the outputs of the zero and single arms of the switching trigger device control the switching of 65 V of the arms (from the first to inclusive) of the memory trigger, and the pulse from the output of the shoulder of this trigger device controls the switching of the {2L + 1) -th memory trigger trigger. After the end of the input (counting) pulse, the switching trigger device switches to a new state in accordance with the new memory trigger state. FIG. 2 shows the successive states of a multi-component element with 2L / -) - 1 stable states (where, 2, 3 ...), defined by the outputs of all the arms of the memory trigger. A multi-stable element with 2jV-f 1 stable states (where, 2, 3 ...) has a speed that is determined by the switching time of the four AND-OR-NOT logic circuits having the minimum power consumption, since in such an element always only three inverters are open (PI-OR-NOT circuits), The subject of the invention is a multistable element with stable states (where, 2, 3 ...), built in a logical basis AND-OR-NOT based on a single memory trigger having stable states and one switching trigger device, synchronized switching memory trigger, characterized in that, in order to simplify the multi-element circuit and reduce power consumption, each memory trigger arm contains two valves — a memory valve, whose inputs are connected to the outputs of all other arms of this trigger, and an information input valve, the first inputs of all of these gates are connected to the input of a multistable element, the second inputs of all odd, except the last, valves of the memory trigger are connected to the output of the zero switching arm Nogo trigger device, and the second inputs of the gates of all even data input latch shoulders memory - a yield of a single arm of the trigger device; the second input of the information input valve of the last memory trigger arm is connected to the output 2M-noto of the switching trngge device; the remaining inputs of the information input valves of all odd, except the last, memory trigger arms are connected to the outputs of all the other arms of this trigger, except for the outputs of the previous adjacent arm, including the last one for the first; the remaining inputs of the information input valves of all the even arms of the memory trigger are connected to the outputs of all the other arms of this trigger, with the exception of the outputs of the previous adjacent shoulder and the last arm; the switching trigger device has zero, one and shoulders, and the zero shoulder contains: a unit input valve, the first input of which is connected to the output arm of this trigger device, and the remaining inputs to the outputs of all even memory trigger arms, except its penultimate shoulder; the input valve of the number 2; V, the first input of which is connected to the output 2L -1 of the shoulder of the switching trigger device, and the second input with the output of the last shoulder of the memory trigger and two memory valves, the first inputs of which are connected to the input of the multistable element, and the second inputs - respectively, with the outputs of the single and 2L-shoulders switching switching device; the unit arm of the switching trigger device contains: iJ, llWnnWiWILIitiVpllV.iv yv-A Jii --- - x - -, - -. valve input all odd shoulders memory trigger except his last shoulder; the input valve of the number 2N, the input of which is connected to the output 2.V-Horo of the switching device trigger shoulder; n the memory valve, the first input of which is connected to the input of the multistable element, and the second input - with the output of the zero shoulder of this trigger device; The 2N-HOQ switching device trigger arm contains: an input “zero” input, the input of which is connected to the output of the zero arm of the switching device, input input “of the unit, the first input of which is connected to the output of the unit arm of this trigger device, and the second input - with the output of the 2L-g a memory trigger; and a memory valve, the first input of which is connected I to the input of a multi-stable element, and the second input to the output of a single arm of the switching trigger device.