RU1786657C - Pulse counter in minimal fibonacci p-codes - Google Patents

Abstract

Usage: the invention relates to computer technology and can be used for ring counting of pulses with a direct representation of the result in minimal P-Fibonacci codes (P 0, 1,2, 3, ...). SUMMARY OF THE INVENTION: The pulse counter in the minimum Fibonacci P-codes contains in each Jth bit a memory element, a common clock bus. To achieve this goal, each memory element is made in the form of a synchronous IK-trigger with direct links to adjacent bits. 4 ill., 4 tab.

Description

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The invention relates to computer technology and can be used for ring counting of pulses with a direct representation of the result in minimal Fibonacci P-codes (0,1,2,3 ...).

A pulse counter is known in Fibonacci P codes, each containing: a T-trigger, whose direct output is the counter information output, a common clock bus ..

The disadvantage of this device is the impossibility of ring counting in the minimum P-Fibonacci codes.

A pulse counter is known in minimum Fibonacci P-codes (, 1,2,3, ...), containing in each bit a memory element, the output of which is the mth information output of the counter, a common clock bus connected to the clock input of each from memory elements. The counter also contains AND elements and an OR element in each of the bits.

The disadvantages of this counter are:

- the complexity of the circuit due to the content of a large number of logical elements in each of the bits;

- low speed due to delayed switching of each trigger due to two-stage AND-OR logic elements;

- low reliability due to a large number of equipment and logical connections between elements.

The purpose of the invention is to simplify, increase speed and reliability.

The goal is achieved in that the pulse counter in the minimum P-Fibonacci codes (.1,2.3 ....), containing in each 1st digit (, 2, .... N) an element

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memory, the direct output of which is the 1st information output of the counter, a common clock bus connected to the synchronizing input of each of the memory elements, the memory element of each 1st bit is made in the form of a synchronous IK trigger, and the direct the output of each 1st trigger is connected to the first l-input of the (i + 1) -th trigger and to the corresponding l-input l + mtP + IJ + lfrq of the trigger, where, 2, ..., n, a n is the integer part numbers (Ni-1 / P + 1), and with the corresponding K-input of the 1st AND (P + 1) -th trigger, where, 2 ..., (NI / P + 1), and the inverse output of each i- ro trigger connected to the corresponding 1st K-in by the moves of the previous P triggers and with - with the K-input (1 + 1} then the trigger.

Nafig, 1-4, the functional diagrams of the counters are presented () at,,,,, respectively, and in tables 1-4 are the conversion codes of the corresponding counters.

The proposed counter (Figs. 1-4) in each 1st digit contains a K-trigger, the direct output of which is the 1st output of the counter. The clock inputs of all the triggers are connected to a common clock bus T. The direct output of each 1 -th IK-trigger is connected to the first I input of the (1 + 1) -th trigger and to the corresponding I input l + m (P + 1) of the trigger, where, 2, ..., n, and n is the integer part of the number ( NI-1 / P + 1), and with the corresponding K-input 1 + 1 (trigger, where, 2, ..., (NI / P + 1), and the inverse output of each 1st trigger is connected to the corresponding I and To the inputs of the previous P flip-flops and for P 0 - with the K input (1 + 1) Trigger.

The proposed counter for various values of P operates as follows.

A single logical potential is applied to the KI and K-inputs of the trigger of the first bit of the counter in minimum Fibonacci codes. At zero initial states of the counter triggers (000000), when the first pulse arrives to the clock buses, regardless of the value of P, the triggers of their first bits are set to single states (100000). The second clock pulse toggles

triggers of the first bits of the counters to the zero state, and triggers of the second bits to the single states (010000). Subsequent clock pulses result in

the formation in the counters of certain codes corresponding to subsequent decimal numbers of a number of natural numbers (3,4,5, ...). However, each of these decimal numbers in the counters, depending on

P values correspond to different code combinations. This is due to the fact that with (Fig. 1, Table 1) the bits of a six-bit counter have weights corresponding to binary numbers (1,2,4,8,16,32), at

(figure 2, table 2) to the numbers of the minimum 1 Fibonacci codes (1,2,3,5,8,13). with (Fig. 3, Table 3) the numbers of the minimum 2 Fibonacci codes (1,2,3,4,6,9), with (Fig. 4, Table 4) the numbers of the minimum 3 Fibonacci codes

(1.2,3,4,5,7) etc.

Claims (1)

Thus, the proposed pulse counter in the minimum Fibonacci P-codes (, 1,2,3, ...) has a simpler circuit due to the absence of logic elements, and as a result has increased speed and reliability. SUMMARY OF THE INVENTION A pulse counter in minimum P-Fibonacci codes (, 1,2,3 ...) containing in each 1st bit (1-1,2, .... N) a memory element whose direct output is the ith information output of the counter, a common clock bus connected to the synchronizing input of each of the memory elements characterized in that, in order to simplify, increase speed and reliability, the memory element of each 1st category is made in the form of a synchronous IK-trigger, with a direct output of each 1st trigger is connected to the first l-input of the (1 + 1) -th trigger and to the corresponding l-input Hm (P + 1) of the trigger, where, 2, ..., n, an is the integer part of the number (NI - 1 / P + 1), and with the corresponding K-input W (P + 1) ro trigger, where M, 2, ..., (Ni / P + 1), and the inverse output of each 1st trigger is connected to the corresponding I- and K-inputs of the previous P-triggers and at - with K-input of the (1 + 1) th trigger, Table 1 Table3 Out 1 Out 2 8 / h.Z Out. 1 Out. 2 Out. 3 8k. 5 Out.6 Table 1 Out 4 jffA / jr.S ffbix; 1786657 L / l 2 8th. W Ex. Bsh.5 ffvx.6 Fig L