SU427346A1 - DEVICE FOR APPROXIMATION OF FUNCTIONS, ASSIGNED BY DIGITAL CODE - Google Patents

Description

device may be

The proposed is applied to a piecewise linear approximation of arbitrary functions defined by digital equidistant vertices. In this case, the setting of the argument is possible in both analog and digital form (nalimer, a sequence of pulses of a unitary code). The result of the approximation is obtained as an analog voltage.

A device for approximating functions defined by a digital code is known, which contains a register whose input is connected to the input of the ordinate code of the device approximation nodes, and the output is connected to the input of the first digital-analog duplicating unit and the input of the second register whose output is connected to the input of the second digital-analogue multiplier block. The outputs of both digital-analog multiplying blocks are connected to the output of the device. The device contains a trigger, a sawtooth generator, a differentiation unit, a delay line, and a digital-to-analog converter, the input of which through a counter is connected to the input of the device argument code.

The disadvantages of the known device are the impossibility of approximation of the functions specified in analog form, and low speed.

The proposed device, in order to extend the functionality and increase the speed, contains two switches, the first inputs of which are connected to the trigger output, the second to the output of the sawtooth generator, and the third to the output of the digital-to-analog converter. The output of the first switch is connected to the first input of the first digital-analog duplicating unit, the output of the second to the first input of the second digital-analog multiplying unit and the input of the differentiation unit, the output of which is connected to the second input of the second register and through a delay with the second input first register.

FIG. 1 shows a block diagram of an apparatus for approximating functions defined by a digital code. FIG. 2 shows diagrams for the operation of the device in the case of approximation of the function when specifying the argument with a digital code; in fig. 3 - diagrams explaining the order of operation of the device in the case of approximation of the function of the time argument.

The device contains registers 1, 2, digital-analogue multiplying blocks 3, 4, digital-to-analogue converter 5 constant voltages, counter 6, sawtooth generator 7, switches 5, 9, trigger

10, differentiating unit P "delay line 12. Input 13 is the input of the ordinate code of the approximation nodes, and input 14 is the input of the unitary argument code. At the 1/5 output of the approximator, an accreted function is obtained in the form of an analog voltage.

Register 1 is designed to receive the parallel ordinate code of the approximated function, transfer to the register 2 the code of the previous value of the approximated function: the function to be used at the time the next code arrives and control unit 5. The input register / connected to the input} 3 devices, and the output with the corresponding inputs. block 3 and register 2.

Register 2 is designed to receive codes from the register and control unit 4.

The D / A multiplier 3 (4) is designed to multiply the in-phase (anti-phase) linear-step (linear) voltage from the output of the switch 3 (9) by the code contained in the / (3) register.

The digital-to-analog converter 5 of the constant (reference) voltage is designed to receive common-mode and anti-phase linear-step voltages proportional to the number of pulses of the unitary argument code supplied to the input of the counter 6. The common-mode and anti-phase outputs of the converter 5 are connected to the corresponding switch inputs 8 and 9, and the input is connected to the output of counter 6.

Counter 6 is used to count the number of pulses of the unitary argument code arriving at summing input 14, " transducer control 5.

Counter 6 and converter 5 participate in the operation of the device only when the functions are approximated, the argument of which is represented by a digital code, in other cases they can be turned off.

The sawtooth generator 7 is designed to generate common-mode and anti-phase linear (sawtooth) voltages proportional to the change in time on the interval under consideration. The common-mode and anti-phase outputs of the generator are connected to the second inputs of switches 5 and 9, cellularly.

The generator 7 participates in the operation of the device in the slice of x setting the argument in analog form.

The switch 8 (9) is designed to switch the input of unit 3 (4) to either the in-phase (anti-phase) output of the converter 5 or to the common-mode (anti-phase) output of the generator 7 depending on the state of the control trigger 10. The control inputs of both switches are connected 1 together and connected to a single trigger output 10.

The trigger W controls the switching of switches 8 and 9. The single input of trigger 10 is connected to the input 16 of the control signal to operate the device with a digital argument setting, and zero to the input J7 of the control signal to operate the device in case of setting the argument in analog form. Differential cascade is designed to differentiate the differential phase-phase stepped-linear (linear)

the voltage corresponding to the end of the coherent interval of approximation and the generation of a signal for the end of the interval of approximation. The input of the differentiating stage is connected to the output of switch 9, and

output - with the setup input of register 2 and the output of the delay line.

The delay line 1/2 serves to delay the interval end signal at time determined by the duration of the transients in register 2 formed when the latter is set to the zero state. The output of the delay line is connected to the register input.

Device on arbitrary for example

J-M. The argument change interval works as follows.

If the argument is represented by a sequence of pulses of a unitary code (Fig. 2), then in the initial state, the registers I and 2 contain the codes P (X;) and P (), the proportional values of the rth and () th nodes, respectively. ordinates of the approximated function | n {, (/ 1,2, 3, ...); the trigger 10 is set to one, which corresponds to the setting of switches 5 and 5 on the switching of the common-mode and anti-phase outputs of the transmitter 5, respectively; counter b is set to zero. When the counter is filled with 6 pulses of the current value of the argument, the number N in it changes, successively acquiring the value of Yu, I, 2 ..., .V ,,, where q is the counter width 6. In accordance with the change in the number L., by The common-mode output of the D / A converter 5 generates an increasing common-mode stepped-linear voltage Uc, proportional to the code L.,:, and an anti-phase output - decreasing anti-phase step-linear voltage and, g, proportional to N.

This voltage, through switch 8, goes to analog input-block 3 and is multiplied by the code P (Xi) stored in register /, resulting in the output of block 5 V

idle mode, we have output voltage and, determined by the formula

and, and .-, and, p (x,),

where A f / i is the price of the youngest bit of block 3;

P is the block width of 3 n 4. Similarly, the voltage / 7 "through switch 9 is fed to the analog input of block 4 and multiplied by the code P (X, - i) stored in register 2, resulting in the output of block 4 in idle mode, there is an output voltage / 2, determined by the formula P - n L / RSU-L (2 pp and t {yi, ij, where Af72 is the lowest bit of the digital-analogue multiplier block 4. V operating mode, i.e., when the outputs of blocks 5 and 4 are connected together and under the condition of equality of their internal resistances, the output voltage of the device at the output / 5, Avl Yupdee, the result of the approximation, is defined as the half-sum of the stresses U and f / 2 {Vyh -2 - ((-) After conversion. P (; (T, -) - I (X - i) Lh I L ,,, P (X /,)} where AC / op-tg is a constant coefficient. This expression is an interpolation polynomial of the first degree. argument for the i-th nodal ordinate of the function being nonconvertible, then we can say that in the t-th segment of the argument change there is a stepwise-linear approximation from b) l; at yV.x 0 to f / out U: when N ,, NmCurrent, t-th, the approximation interval ends at the moment of overflow of counter 6, which occurs in each interval when entering (N, n +) - TO pulse. If the argument is presented on the considered approximation interval by a paraphase linearly from, varying (cc) voltage (Fig. 3), then in the initial state in the registers I and 2, the codes P (Xl) and P (Xg), PROPORTIONAL the values of the m / s and (i-1) -th nodal ordinates of the approximated function; the trigger 10 is set to the zero state, which corresponds to the installation of non-switches 5 and 5, for switching, respectively, the in-phase and anti-phase outputs of the generator 7 of a l-shaped voltage. Counter 6 and converter 5 do not participate in the operation of the device and iB can be switched off. As the common-mode linearly varying voltage Um Um t increases from zero to maximum Ucm Uon-T and the antiphase linearly varying voltage decreases simultaneously (UP op (-t) from the maximum value Unm Uou G to zero, where 0 Г is the current time value, and G - period, voltage / s through switch 8 enters the input of block 3 and is multiplied by code P (Xi stored in register 1. As a result, the output of block 5 in idle mode has an output voltage t / i, which is determined by the formula U, U, .U, .P (X:}. Similarly, the voltage Un through the switch 9 enters the same input of block 4. In idle mode, we have output voltage u, Uon (T t). Sch A and, P (X,). In operating mode, i.e. with connected outputs of blocks 3 and 4, output The approximation voltage of the output approximator 15 is defined as the half-sum of the voltages / and Uz t / 3 .. (t /, + i / 2), (/) - P №-i) i + + TP (X: -4 }}. This is also an interpolation polynomial of the first degree, and the device realizing this polynomial, and in the case of the analog representation of the argument, is an approximator, the i-th approximation interval ends at time t T. Differentiated The overlap (trailing edge) of the antiphase sawtooth voltage from the output of the differentiating stage enters the setup input of register 2 and sets it to the zero state, while the pulse from the output of the differentiating cascade delayed in delay line 12 sets the register to zero. iflpii, this transfers the code P (X /) to register 2, and the register P (Aj + i) of the following (i + l) -ii ordinates is entered into register 1. On the (t-M) -M interval and on all subsequent approximator works in a similar way. The subject of the invention is a device for approximating functions defined by a digital code, containing a register, the first input of which is connected to the input of the ordinate code of the approximation device, and the output is connected to the second input of the first digital-analogue duplicating unit and the first input of the second register, the output of which is connected to the second input of the second digital-analog duplicating unit; the outputs of both digital-analog multiplying units are connected to the output of the device, a trigger, a sawtooth generator, a differentiation unit, a delay line and | digital-analog (a new converter whose input through the counter is connected to the input 1 of the device argument, characterized In order to expand functionality and speed up, it contains two non-switches, the first inputs of which are connected to the trigger output, the second to the output of the sawtooth generator, and the third to the output of the an analog-to-digital converter; the output of the first switch is connected to the first input of the first digital-analog multiplier; with the second input of the first register.

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