SU424188A1 - FREQUENCY-PULSE MULTIPLE-PERFORMANCE DEVELOPMENT - Google Patents

Description

one

The invention relates to computing and measuring technology. It can be used as a mathematical node, performed its multiplying-dividing operation, or as a device for frequency amplification.

A device of similar purpose is known, comprising an open multiplying-dividing device, a reversible counter, a code-to-voltage converter, a controlled frequency generator, a dynamic error analyzer that includes a reversible counter, a group of impulse-like coincidence circuits, a memory device consisting of a pulse counter and a matching circuit; and a subtractor. It is characterized by a longer transition time, determined by the parameters of the tracking system (aperiodic link).

The aim of the invention is to increase the speed of the device and obtain the instantaneous (period) value of the output pulse frequency sequence. This is achieved by the fact that the device contains keys, an integrator and a block for difference of periods, whose inputs are connected to the input frequency bus, the output of the OR circuit and the output of the reversible counter, and the outputs are connected to the second input of the first AND circuit The schemes “And, the second inputs of which are connected to the output of the time calibrator; the outputs of the fourth and fifth circuits And are connected to the first inputs of the first and second keys, respectively, the second inputs of which are connected to the output of the division block by code; the output of the first switch is through the second inverter, and the output of the second switch is directly connected to the inputs of the integrator, the output of which is connected to the inputs of the controlled frequency generator and voltage dividing unit code. The drawing shows a block diagram

devices.

The device comprises an integrator 1, a voltage dividing unit with a code 2, consisting of a DC amplifier 3 and a code converter into a voltage 4; pulse counter 5; controlled frequency generator 6; inverters 7 and 8; keys 9 and 10, time calibrator 11; reversible counter 12; schemes “And 13, 14, 15, 16 and 17, schemes“ OR 18 and 19; multiplying block 20; a period difference selection block 21, comprising three flip-flops 22, 23 and 24, And 25 and 26 circuits, a delay element 27, and a pulse shaper 28. In the device of the input frequency bus 29 (Fi, F and FZ), there are connections to the inputs of multiplying-separating block 20. In addition, the frequency bus

Pi is connected to the unit installation inputs of the flip-flops 22 and 24, the inputs of the circuits "And 14 and 15 and through the delay element 27 - to the input of the circuit" And 25. The output of the multiplying block 20 through the circuit "And 13 is connected to the summing input of the reversible counter 12 and the input of the counter impulses 5 whose outputs of the flip-flops are connected to the code buses of the voltage dividing unit to code 2, the output connected to the inputs of keys 9 and 10. The key 10 output is connected to one VH10DO | M of the integrator 1, which is connected to the output of another input through the second inverter 8 9, and exit - with the inputs of the voltage dividing unit at code 2 and the adjustable frequency generator 6. The output of the controlled frequency generator 6 is connected to the output frequency bus FZ, the input of the time calibrator 11, the subtracting input of the reversing counter 12, the unit outputs of the trigger are connected to the inputs of the first circuit “OR 18, the output connected to the input of the circuit“ AND 25 and the input of the nerve inverter 7. The output of the latter through the third circuit “AND 15 is connected to the input of the circuit“ OR 19, the output of which is connected to the buses of setting the pulse counter 5 to zero to 12 and the second input of the OR 19 circuit is connected to the output of the second circuit AND 14, which is connected to the single output of the senior trigger of the reversible counter 12 and through the pulse shaper 28 to the input of the circuit AND 26 and the single installation input of the trigger 23. Zero the setup input of the trigger 23 is connected to the output of the circuit “AND 25 and the zero installation input of the trigger 24, in which the unit output is connected to the input of the first circuit“ AND 13. In addition, the single output of the trigger 23 through the circuit “AND 26 is connected to the zero installation input of the trigger 22 , which zero output is connected to the input of the circuit “AND 16”, which by the output is connected to the input of the first key 9, and the second input to the output of the time calibrator AND and the input of the fifth circuit “And 17, the second input of which is connected to the zero output of the trigger 23, and the output - to the input of the second key 10.

Consider the operation of the device for cases where the input frequency A increases and decreases.

In the steady state, the number of output frequency pulses over a period is equal to the number of pulses in the Ni Fa / Fz bundle, and by the time the frequency pulse i arrives, the reversing counter 12 will be reset. In this case, the triggers 22 and 23 are in the one state, and the trigger 24 is in the zero state. Therefore, the output frequency pulses F do not pass through the circuits AND 16 and 17 to the input of switches 9 and 10, i.e. the feedback circuit of the integrator 1 is broken. Setting counter 5 to the zero state is originating through the AND 15 circuit, which is opened by the inverted potential from the OR 18 output.

connected to the single outputs of the trigger of the reversible counter 12, i.e. with the reversing counter reset to zero 12, the output potential of the first inverter 7 will be.

If period 7 increased and became equal to .r.-i-A7 then when the reversible counter went from state 00 ... 00 to state 11 ... 11 (which corresponds to a code value of -1) from the non-output potential at the output of the high trigger the reversible counter 12, the trigger 22 is set to the zero state, and to the input of the key 9 from the output of the time calibrator I the pulse frequencies FZ are received with the duration To. The average voltage value at the output of the key circuit 7 is equal to

 AG.GO

6s „

 t - int

wed

where Ki is the constant amplifier factor

current;

Kz is the coefficient of vitality; Kypt - voltage of the integrator;

Ni is the number of pulses in the “pack. Thus, before the arrival of the FI frequency pulse, i.e., for the time (+ AG), the device that reproduces the quadratic dependence is included at the feedback of integrator 1, and the voltage removed from the integrator is inverted twice. The law of voltage variation at the output of the integrator 1 is determined from the expression

f / o

CT -

W.

1 + .t + KtRC

The incoming frequency pulse fi sets the trigger 22 to one state, thereby closing the fourth AND 16 circuit and breaking the feedback of the integrator 1. This same pulse, passing the second AND 14 circuit, sets the reversible counter 12 and the pulse counter to zero. 5. The resolving potential on the second circuit, AND 14, is fed from a single counter 12, which is in a single state with a negative number in a reversible counter. When reducing the neorod

1H - IC.T T

By the time the FI frequency pulse arrives, a certain number b of unlisted impulses will remain in the invert. counter 12. Then the schemes "And 14 and 15 will be closed and counters 12

and 5 will not be reset. The pulse frequency Fi, delayed in the delay element 27, through the open circuit "And 25 is attached to the zero setting inputs of the flip-flops 23 and 24. The time interval {-AH) will be equal to Ar 6-7z current and will end when the reversing counter 12 goes from state 00 ... 00 to 11 ... 11. An impulse generated by non-erect will set trigger 23 to one state, but will not pass AND 26, since there is a delay in setting trigger 23.

Integrator Output Voltage

and.

nt

dg

one -

C. The next pulse of frequency F sets the trigger 24 to the one state, i.e., allows the passage of the signals through the AND-17 circuit, and the passage of the AND-14 circuit sets counters 12 and 5 to the zero state. The impulse fi delayed in the delay element 27 does not pass the AND 25 circuit and the trigger 23 remains in one state.

Thus, the device allows to reduce the frequency / i to the end of the first period of the modified frequency to obtain the required value of the output frequency F, and with increasing input frequency F - the exact value of the output frequency after two periods of the frequency Fi.

Subject invention

The pulse-frequency multiplying-dividing device, containing, its multiplier-separating unit, the inputs of which are connected to buses | input frequencies, and the output is connected to the first input of the first “And circuit, the output of which is connected to the first input of the reversible counter and the first input of the pulse counter, the outputs of which connected to the inputs of a code division dividing unit;

controlled frequency generator, the output of which is connected to the output of the device, the input of the time calibrator and the second input of the reversible counter, the outputs of which are connected to the first input of the second AND circuit and the inputs of the first OR circuit, the output of which through the first inverter is connected to the first input of the third circuit And, the second inputs of the specified circuits “And are connected to the bus of the input frequency, and their outputs through the second circuit“ OR connected to the second input of the pulse counter and the input “setting the reversible counter to zero; the second inverter and the circuit "And, otlichuush, it is that, with

To improve speed, it contains keys, an integrator and a block for difference of periods, the inputs of which are connected to the input frequency bus, the output of the OR circuit and the output of a reversible counter, and the outputs are connected to the second input of the first AND circuit. Circuits "And, the second inputs of which are connected to the output of the temporary calibrator; the outputs of the fourth and fifth of the schemes "And connected

the first inputs of the first and second keys, respectively, the second inputs of which are connected to the output of the voltage dividing unit; the output of the first switch is through the second inverter, and the output of the second switch is directly connected to the inputs of the integrator, the output of which is connected to the inputs of the controlled frequency generator and the voltage dividing unit.