SU410464A1 - - Google Patents

Description

one

The invention relates to "automatic and communication".

Known shift registers on the two-input logic elements "OR-NOT, each bit of which consists of two triggers with logic circuits at the input of each of them.

Known shift registers contain in each bit a large number of logical elements “OR NOT.

The proposed shift register on the two-input elements "OR-NOT is different in that, in order to simplify the circuit, each bit is built on two triggers, each of which is executed on two elements" OR- the output of the first element "OR-NOT the first trigger is connected" the input of the second element “OR-NOT the second trigger, to the outputs of the second element“ OR-NOT both triggers are connected capacitances, the inputs of the first elements “OR-NOT both triggers are connected respectively to the buses of the first and second cycles, and the input of the second element“ OR NOT trigger by The key to the receiving bus.

FIG. 1 is a diagram of one bit of a given shift register; in fig. 2 is a time diagram, based on the principle of operation of one bit. ;

Input 1 of each bit is connected to the input of the element "OR-NOT 2, the output of element 2 - with the inputs of the elements" OR-NOT 3, 4, the output of element 3 - with the input of element 2 and the capacity 5.

Input 6 is associated with element 3, the output of the element "OR-NOT 4 - 00 (the INPUT of element 7 and the capacitor 8, the output of element 7 is with the input of element 4 and output 9 of the whole discharge, input 10 of this discharge is with the input of the element" OR NOT 7.

Thus, each register bit consists of two triggers (the elements “OR — NO 2, 3 and the elements“ OR — NO, 4, 7) with

capacitors connected to their inputs (5 and 8, respectively).

A signal b is applied to the input 1 of each bit (Fig. 2), which is the inverse of the signal a. Input 6 (Fig. 1) provides a signal

records b. The output signal g is removed from output 9 of this bit. If there is no record (signal b is equal to zero), the signal d from the output of element 3 is equal to one. In this case, the signal e from the output of element 2 is zero, and the trigger

with elements 4, 7 it is set so that at the output of element 7 is zero, and at the output of element 4 is one (signals r and h, respectively). Input 6 is supplied with a record (signal b is equal to one) in phase with a pulse

signal b. Deviation of the front and backward fronts are allowed. In this case, the signal d becomes equal to zero and the signal e remains equal to zero, since the signal b is equal to one. When the signals of the biv become equal to zero, the trigger with the elements 2, 3 is in an unstable state. However, capacitance 5 delays the appearance of the unit at the output of element 3, and the trigger is set to a state in which the signal e of element 2 is equal to one, and from the output of element 3 is zero.

Then, when the signal b becomes equal to one, the trigger with the elements 2, 3 returns to the initial state (in the absence of the next write pulse).

Thus, when recording one unit, the output of element 2 produces a signal e, equal to one, in phase with the pulse of signal a and shifted by half the period of the clock signal. The trigger with elements 4, 7 is supplied with a clock signal a and a recording signal e, the same as with a trigger with elements 2, 3, but shifted by half the period of the clock signal.

The trigger with elements 4, 7 acts like a trigger with elements 2, 3, and the signal from the output of element 7 is shifted by another half of the period of the clock signal. Consequently, the output signal r is shifted relative to the recording signal 8 by the period of the clock signal and can be used as a recording signal for the next register bit.

Subject and discoveries

The shift register on the two-input “OR-NOT, OTL IChA elements, in order to simplify the circuit, each register bit is built on two triggers, each of which is performed on two“ OR-NO ”elements, with the output of the first element “OR NOT NOT of the first trigger is connected to the input of the second element“ OR — NO (Second trigger, to the outputs of the second element “OR — NOT both triggers are connected to the capacitance, inputs of the first elements“ OR — NOT to both triggers, respectively and the input of the second element "OR NOT NOT the first trigger is connected to the receiving bus.

GO,