SU1585805A1 - Device for determining extrema - Google Patents

Abstract

The invention relates to computing and can be used in hydro and radar, acoustics and medicine, for processing speech signals and in adaptive systems. The purpose of the invention is to improve accuracy. The device contains two registers 1 and 11, block 2 comparison, trigger 3, three elements NOT 4, 5 and 8, element OR 6, analog-digital converter 7, generator 9 clock pulses, unit 10 synchronization, element AND NOT 12, two multiplexer 13 and 14. 1 Il.

Description

The invention relates to special means of digital computer technology intended for signal analysis and can be used in hydro- and radiolocation, acoustics and medicine, for processing speech signals and in adaptive systems.

The purpose of the invention is improving accuracy.

The drawing shows a structural diagram of the proposed device.

The device for determining extrema contains the first register 1, block • 2 comparisons, trigger 3, first 4 and second 5 elements NOT, element OR 6: analog-to-digital converter 7, third element NOT 8, clock generator 9, synchronization block 10 , second register 11, AND-NOT 12 element, first 13 and second 14 multiplexers, mode selection input 15.

The device for determining extrema can work in two modes. We consider each mode separately from the first mode. In the initial state, a signal with a voltage level of logic 1 is applied to input 15 of the mode selection. At the initial time, the state of the first 1 and second 11 registers can be any, and for simplicity of understanding, let us assume that they are in the zero state. Then, with the appearance of the synchronization signal of the gating signal at block 10, the output of Equal to block 2 of the comparison, a signal of strict equality of numbers appears in the first 1 and second 11 registers. This signal, acting on a rising edge at the trigger synchronization input. 3, switches it to the opposite state, since its inverse output is connected to. information input, forming the functional inclusion of the D-trigger in the T-trigger mode (division by two). Assume that the initial state of trigger 3 is zero. Then, after exposure to the first gating signal jq, trigger 3 is set to a single state. At the output of the AND-NOT 12 element, a signal is generated with a voltage level of logical 0, which, acting on the first input of register 11, 55, inverts the output (State of the second register 11 ". Thus, at the second information 'input of the comparison unit 2 there is a number determined by units in all digits of the second register 11.

. The next phase of the operation of the device begins with the formation at the output of the synchronization unit 10 of the recording signal of the numerical equivalent of the input signal of the analog-to-digital converter 7 in the first register 1. The presence of two phases of the operation of the device improves the stability of work and eliminates the ambiguity of the state of the elements, since the possibility of racing is eliminated. Assume that the number written in the first register 1 is less than 2 ^P (n is the number of bits). Then, when a gating signal appears, a signal is generated at the output of Less than block 2, which, acting on the installation input of trigger 3, confirms its single state. At the same time, at the output of the first 13 multiplexer there is an address at which the passage of the signal from the Less output through the second 14 multiplexer is prohibited, and therefore, the output state of the first register 1 is not rewritten to the second register 11. When the numerical equivalent of the input signal reaches the maximum (2 * ¹ ) value (increasing the amplitude value), the first and second inputs of block 2 contain the same (equal) numbers and when the gating signal appears, a signal is generated that switches trigger 3 to the zero state. At the output of the AND-NOT 12 element, a signal is formed with a voltage level of logical 1, which leads to the establishment of a direct number at the output of the second register 11. In the future (a decrease in the amplitude value of the input signal), a minimum number is present at the information output of the device, and a signal indicating the direction of change in the amplitude value of the input signal is present at the output of the trigger. 3. At the same time, switching trigger 3 from one state to another indicates the moment of reaching the maximum or minimum value of the input signal. If there is flat sections in the input signal form with minimum or maximum (trapezoidal) amplitude values, a series of pulses appears at the output of Block 2, the number of which is proportional to the time interval of these sections. This mode

1585805 'is effective for filtering and processing various types of pulse sequences. When analyzing the input signal form, period and amplitude of which | Hornes are functions of time; the second mode is used.

The second mode. Consider the operation of the device, assuming that at the initial time, the input 15 of the mode selection receives a signal with a voltage level of logic 0, the first 1 and second 11 registers and trigger 3 are in the zero state. A signal with a voltage of logical 0, arriving at the second input of an AND-NOT 12 element, <ensures the formation of a voltage level of logical 1 at the output of an AND-NOT 12 element and thereby sets the second register 11 to the information transfer mode in direct code. In addition, a signal with a logic level of 0 sets the first multiplexer 13 to the address inputs of the non-inverted paraphase signal from the trigger 3 to the address inputs of the second multiplexer 14, which provides the transmission of signals from the outputs of the comparison unit 2 to the output of the second multiplexer 14 for writing operation The new number in the second register is 11.

Suppose that the output is analog. go-to-digital converter 7 pri-. there is no number ^ other than zero. and with the appearance of the write signal synchronization block 10, the output number of the analog-to-digital converter 7 is recorded in the first register 1. At the second input of the comparison block 2, there is a number that is larger than the number at the first input of this' block 2 coming from the output of the second register 11. With the appearance of the gating signal at the output of More than block 2, a pulse appears and, acting on the reset input of trigger 3, sets (in this case, confirms) its zero state. Trigger paraphase output. 3, passing through the first multiplexer 13, forms at the input of the second multiplexer 14 an address that allows the passage of a pulse from the output of More than block 2. The output signal of positive polarity from the output of the second multiplexer 14 is fed to the input of the second element NOT 5 and on the leading • edge (ΐ ⁰¹¹ ) the output signal of the element NOT 5 is recorded in the second register 11 of the number that occurs, 'is at the output of the first register 1.

To eliminate ambiguity (digital noise) in the second phase of the device’s operation, the mode of generating a confirmation signal for writing a number to the second register 11 is used, which, passing through the first element NOT 4 and the OR element 6, sets block 2 to its original state, and therefore, at the input of the block 2 no gating signal. After writing a new number to the 'first register 1 at the inputs of block 2 comparison, a new combination of numbers appears, and there is no gating signal. With the arrival of the next pulse from the generator 9 clock pulses, the synchronization unit 10 switches to the mode of generating a gating signal. Further, this process is repeated under the condition that the number written in the first register 1 is greater than the number in the second register 11. If at some point in time it turns out that in the first register 1 there is a number less than in the second register 11, then, when the comparison of the gating signal appears at the input of block 2, a signal is generated less at its output, indicating the order of change in the digital equivalent of the input signal. This signal, arriving at the installation input of trigger 3, sets it into a single state, and paraphase ^. the output signal from the trigger 3, passing through the first multiplexer 13, sets the address at the input of the second multiplexer 14 for passing through the second input of its signal generated at the output of Less than block 2. The output signal of the second multiplexer 14, passing through the second element NOT 5, records a new number (located in the first register 1) in the second register 11, the moment the trigger 3 is switched to a single state determines the temporal position of the upper extremum of the input signal. In the process of analyzing the input signal at the output of Less than the comparison unit 2, a pulse appears that confirms the single state of trigger 3 until the number in the first register 1 is less than the number in the second register 11. At the moment when the number in the first register 1 turns out to be more than the number in the second register 11, at the output of More than block 2, a pulse is formed that sets trigger 3 to the zero state and thereby fixes the current lower 'extremum of the input signal. If it turns out that the input signal has a flat part in any of its areas and in time is more than two periods of the pulse sequence of the pulse generator 9, then at the output of Block 2 there is also a series of pulses, the number of which is proportional to the flat portion of the input signal.

Claims (1)

Claim. A device for determining extrema, containing two registers, a trigger and an OR element, distinguishing e with that in order to increase ^; accuracy, a clock generator, a synchronization unit, a comparison unit, an NAND element, three NOT elements, two multiplexers 25 and an analog-to-digital converter, the information input of which is the information input of the device, the output of the analog-to-digital converter, is inserted into the information jq input is in the first register, the output of which is connected to the first information input of the comparison unit and with the information input of the second register, the information output of which is the information output of the device, connected to the second information input of the comparison unit, the output of which is also connected to the trigger synchronization output, the direct output of which, which is the * output of the indication of the moment of occurrence of the extremum, is connected to the first information input of the first multiplexer and to the first input of the AND-NOT element, the output of which is connected with an input-inversion of the second register, the record confirmation output of which through the first element is NOT connected to the first input of the OR element, the output of which is connected to the reset input of the synchronization block, the first input of which is connected to the output of the clock generator, the first output of the synchronization unit is connected to the clock input of the register, the second output of the synchronization unit is connected to the gating input of the comparison unit, the output of which is less than connected to the first information input of the second multiplexer and to the installation input of the trigger, whose inverse output is connected to the information input of the trigger and to the second information input of the first multiplexer, the first and second outputs of which are connected respectively to the first and second the address inputs of the first multiplexer, the output of which through the second element is NOT connected to the recording input of the second register, the third output of the synchronization unit is connected to the second input of the OR element, the input of the device mode selection is connected to the second input of the AND-NOT element, with the first address input of the first multiplexer and through the third element NOT with the second address input of the first multiplexer, the output of the More comparison block is connected to the trigger reset input and to the second information Input of the second multiplexer.