SU410388A1 - - Google Patents

Description

one

This invention relates to the field of computing.

A known device for shifting information, containing a shift register in which the first outputs of each bit are connected via the corresponding elements of the first group of interdigit information transfer to the first input of the next bit, and the outputs of the elements of the second group of interdigit are connected to the second inputs of the shifting elements information transfer, and the outputs of each bit are connected to the corresponding inputs of the control circuit, not reliably.

The purpose of the invention is to increase the reliability of the device.

This goal is achieved by the fact that the proposed device additionally contains a de-embossing device, the first outputs of which are connected to the first inputs of the corresponding elements of the second group of inter-bit information transfer, and the second outputs to the second inputs of the corresponding elements of the first group of inter-bit information transfer, counter, the first output of which is connected to the first input of the decoder, the trigger, the OR element, and the coincidence circuit. The third inputs of the elements of the AND of the first group of interdisciplinary information transfer are connected to the ge + 1 input of the control circuit and to the first inputs of the first, second, and third coincidence circuit. The first output of the control circuit is connected to the first input of the fourth coincidence circuit and the second input of the first coincidence circuit, to the third input of which the first trigger output is connected. The second output of the trigger is connected to the second input of the second coincidence circuit, to the third input of which the second output of the control circuit is connected. The outputs of the first and second coincidence circuits are connected to the corresponding inputs of the first OR element, the output of which is connected to the second inputs of the AND elements of the second group of inter-bit information transfer. The output of the third coincidence circuit is connected to the input of the counter, the second output of which is connected to the second input of the fourth coincidence circuit, the output connected to the trigger input. The outputs of the last elements “And the first and second groups of interdisciplinary information transfer are connected to the inputs of the second element“ OR.

In the device, in the event of a failure in any of the bits, the correct information is provided from the numerical output of the device by localizing the fault location, determining its type (the fault translates "I to" O or "O to" 1) and then introduces a correction to the information generated by shifts in shear bits

register. The introduction of the correction or its absence depends on the place of the incompetence, its type and information issued by the control circuit, and is carried out by applying the recording signal "1 to the register bit, which should receive information from the output of the faulty bit. In this case, the connection of the faulty discharge and the subsequent discharge is broken.

The drawing shows a block diagram of the proposed device for shifting information, where indicated: 1 - the first input intended for supplying a serial code or a first bit of a parallel code to the device; 2 — second inputs transferring a parallel code to the device; 3-6 are the shift register bits; 7 - the third input, which provides the transfer of clock pulses to the device; 8 - element 9 - the first exit intended for serial output of shifted information; 10 - the first group of elements “And interdisciplinary information transfer; 11 is a control circuit that performs error detection by modulo control (2,3 ...); 12 - the second output intended for transmitting the signal “error; 13 - the fourth entrance; 14 - trigger for fixing the type of failure: "1 in" O or "O in 15, 16 - coincidence circuits; 17 is a counter; 18 is a coincidence circuit; 19 is the fifth input intended for transmitting the diagnostic test signal, 20 a coincidence circuit; 21 - the decoder; 22 — element 23 — a third output for transmitting a diagnostic end signal; 24 - the second group of elements “And interdischarge transmission of information providing the output of a correction signal when an error is detected.

The device works as follows.

The numerical information to be shifted enters the device either as a serial code at input 1, or as a parallel code at input 1 of the first bit and inputs 2. A record of the parallel-bit code is made simultaneously in all bits 3-6 of the register . The information shifts are made when the clock shift device is fed to the third input 7 of the device. The output of the shifted information is carried out through the element "OR 8 to the first output 9 of the device. Interdividing the transfer of information during the shifts is carried out through the elements" AND of the first group of interdisk transfer of information 10, the first inputs of which receive numerical information, and the second clock pulses. During the operation of the device, the circuit control I checks the shifted information modulo, the value of which is chosen depending on the required control efficiency and a number of other requirements. When an error is detected, the control circuit 11 outputs to the second output 12 of the device a signal “error. If the error occurred as a result of a failure, then if you repeat the entire cycle of the device, starting with re-submitting information to its input, the information shifts correctly. If the error is repeated, it indicates the presence of a failure in one of the bits 3-6 of the register. In this case, the device stops operating in the main mode and a diagnostic check is performed in order to localize the location of the malfunction and its type, i.e., it sets whether the failure "1" to "O or" O to "1.

The diagnostic test is performed as follows.

A signal is set to the fourth input 13 of the device, which sets the trigger 14 to a state in which the enabling signal is fed to the first input of the matching circuit 15. Then, code 00 ... 0 is set in bits 3-6 of the register. If one of the bits has a failure of type “O to” 1, then when setting code 00 ... O, control circuit 11 detects an error, since In one of the bits, the state “1. The error signal from the first output of the monitoring circuit 11 is fed to the first input of the matching circuit 16, the second inputs of which are connected to the second outputs of the counter 17 to detect the 00 ... 0 state in it. Since the initial time in the counter contains the code 00. Oh, then the output of the matching circuit 16 produces a signal that flips the trigger 14 to a state where the enabling signal arrives at the first input of the matching circuit 18. If in one of bits 3-6 of the register there was a failure of type "1 in" O, then the installation of the code "00 ... O occurs normally, and the trigger 14 retains its state, which it occupied after submitting to the fourth input 13 signals. Thus, the state of the trigger 14 corresponds to the type of failure.

To localize the malfunction of the bit, a diagnostic check is sent to the fifth input 19, which is permissive for the coincidence circuit 20 and prohibiting for the decoder 21. Then the device 1 is fed to input 1 and a series of clock signals to input 7. The clock signals arriving at the first elements of < RTI ID = 0.0 > 10 < / RTI > carry out a sequential promotion of "1 by bit 3-6 register. In addition, the clock signals arrive at the clock input of the control circuit 11 and the element “And 20. When clock signals are applied to the input of the control circuit 11, it checks the state of bits 3 to 6 of the register and generates signals“ correctly at its second output or signal “Mistake on the first. The clock signals input to the open element < 20 are passed through it to the input of the counter 17. As a result, the counter 17 counts the number of clock pulses and, therefore, the code generated in the counter 17 is equal to the digit number code 3- 6 of the register in which “1. If in one of bits 3-6 of the register there was a failure of type “O in“ 1, then in each shift cycle at the first output of the control circuit 11 there will be a signal “error until shifted“ 1 will not go into the failed bit. In this case, at the second output of the control circuit 11, a signal is generated that is “true”, which passes to the third input of the coincidence circuit 18, the first input of which has already received the enable signal from the trigger 14, and the second to the clock signal. As a result, the output of the circuit 18 forms a signal that passes through the second element OR 22 to the third output 23 of the device, which indicates the end of the diagnosis.

If in one of the bits of the shift register there was a failure like “1 in“ O, then in each step of the shift at the second output of the control circuit 11 there will be a signal “as long as it is shifted“ 1 does not go to the failed digit. In this In the case of the first output of the control circuit AND a signal is generated, an error that passes to the input of the coincidence circuit 15. As a result, a diagnostic end signal appears at the third output 23 of the device. Thereafter, the "diagnostic test" signal from input 19 is removed and the output of clock pulses to input 7 is terminated.

Since the signal was removed, the diagnostic test, which is forbidding for the decoder 21, is: decoding the code contained in the counter, 17.

After each cycle of information shift, the control circuit AND performs a check and, depending on the presence of the detected error and the type of failure, the next cycle is or does not correct the information contained in the bit following the number after the failed one. Correction is made by issuing a pulse through a coincidence circuit of 15 or 18, the second element OR 22 and one of the elements AND 24 at the input of the corresponding bit or the first element OR 8. A corrective impulse is issued in the following two cases: if there is a failure of the type “About in” 1 control circuit 11 did not detect an error in some cycle or, if there was a failure like “1 in” About the control circuit detected an error in some cycle.

Subject invention

A device for shifting information containing a shift register in which the first outputs of each bit are connected to the first inputs of the register bits through the corresponding elements of the first group of inter-bit information transfer, and the elements of the second group of inter-bits are connected to the second inputs of the register bits information transfer, and the outputs of each bit are connected to the corresponding inputs of the control circuit, characterized in that, in order to increase the reliability of the device, it additionally contains a decoded p, the first outputs of which are connected to the first inputs of the corresponding elements “And the second group of interdigit information transfer, and the second outputs - to the second inputs of the corresponding elements“ And the first group of interdisk information transfer, the counter, the first output of which is connected to the first input of the decoder, trigger , the elements of "OR and match schemes; the third inputs of the And elements of the first group of interdisciplinary information transfer are connected to the l + 1 input of the control circuit and to the first inputs of the first, second, and third coincidence circuit; the first output of the control circuit is connected to the first input of the fourth coincidence circuit and the second input of the first coincidence circuit, to the third input of which the first output of the trigger is connected, the second output of which is connected to the second input of the second coincidence circuit, to the third input of which the second output of the control circuit is connected; the outputs of the first and second coincidence circuits are connected to the corresponding inputs of the first OR element, the output of which is connected to the second inputs of the AND elements of the second group of inter-bit information transfer; the output of the third coincidence circuit is connected to the input of the counter, the second output of which is connected to the second input of the fourth coincidence circuit, the output of which is connected to the trigger input; the outputs of the last “And” elements of the first and second groups of interdisciplinary information transfer are connected to the inputs of the second element “OR.