SU374601A1 - SYNCHRONIZER OF TWO COMMANDS "2SUSIONION"; iU: .-; :: rT. ^ Ri ,,. Tr | -K :: - 'r;.! V ^: - Google Patents

Description

The invention relates to electrical measuring computers and can be used in the construction of frequency-digital devices, in particular devices, the measurement of which is performed in the adjacent intervals.

A device is known which synchronizes the pulses of two independent frequencies from one frequency to the pulses of the clock (reference) frequency. The device contains a clock trigger and two identical paths, each of which consists of a trigger, a coincidence element and a one-shot.

The device has the disadvantage that the order in which the output pulses occur depends not only on the order of arrival of the input frequency pulses, but also on the state of the clock trigger. If, with the arrival of a single pulse of the input frequency from the output of each path, it is necessary to obtain a series of pulses that control a series of sequential operations, the path triggers can be replaced with frequency dividers or registers. However, the implementation of one of the sequence of operations ne excludes the implementation at the same time another.

These disadvantages do not allow using the device when it is necessary to take into account the sequence of incoming commands and prohibit the execution of one of the sequences of operations for the duration of the second.

To expand the functionality, the proposed device contains two OR circuits and a memory trigger, whose inputs are connected to two OR circuits, and the outputs to the third inputs of the corresponding AND circuits, the inputs of the first OR circuit are connected to the single outputs of the triggers, and

the second scheme "OR - with zero outputs of these triggers.

The drawing shows a diagram of the proposed device. The device contains triggers 1 and 2, schemes

“AND 3 to 4, schemes“ OR 5 and 6, memory triggers 7.

If the synchronizer synchronizes two separate commands, points a and b in the drawing are connected. If it is necessary to synchronize two independent sequences of operations, between points a and b it is necessary to establish dividers or registers, the number of states of which is determined by the number of necessary operations.

For simplicity, consider the case of synchronization of two independent commands (points a and b are connected).

The individual units of the device are interconnected by the following functional dependencies. Commands A and B are fed to the setup inputs of the flip-flops / and 2, the second inputs of which are supplied with pulses of the clock frequency / t from the output of the circuits I 3 and 4. The passage of frequency pulses / t through circuits "And 3 and 4 depends on the state of memory trigger 7 and sync trigger 1 and 2. The left outputs of trigger I and 2 are connected to the inputs of the circuit" OR 5, the output of which is connected to the left trigger input of the memory 7. The right inputs of the flip-flops 1 and 2 are connected to the inputs of the OR 6 circuit, and its output to the right-hand setup input of the memory trigger 7. The Lt output command corresponding to the L input command is removed from the U right trigger output, the W command is left trigger output 2.

The operation of the device is as follows.

In the initial position, the trigger / and is in the state "O, trigger 2 - in the state" 1. (We assume that the state “O is characterized by the presence of a zero potential trigger on the right exit, the state“ b - of a positive potential). The zero potential from the moral output of the trigger 7 blocks the passage of pulses of the clock frequency / t through the PI 3 circuit to the trigger input /. Similarly, the zero potential from the left output of trigger 2 blocks the passage of pulses of the clock frequency / t through the AND 4 circuit to the input of trigger 2. Memory trigger 7 can be in any state. The device is in a state of waiting for incoming commands A c B.

Three options are possible for these commands: the commands do not overlap one another (for example, command A arrives at the input of trigger 1 at the moment when the circuit is in its initial waiting state); the commands are superimposed one on the other (for example, command B appears at the moment when the formation of the command Lt is not completed, due to the appearance of command L); L and B commands appear simultaneously.

Consider the first case of the device. Let the memory trigger 7 be in the state "1. Therefore, from its first output, the positive potential of "1. The arrival of a comaid L will cause a one-to-zero transition at the right input of the trigger /, which causes the latter to roll over to the state 1. The potential from the right output of this trigger is applied to one of the control inputs of the "I 3" circuit and to the left output of the device. A zero potential is applied to both inputs of the OR 5 circuit. This leads to setting the memory trigger 7 in the “O” state and, consequently, to potential supply “1” from the left output of the memory trigger 7 to the second control input of the “I 3” circuit. will pass to the left input of the trigger / and set it to the state "O. The resulting zero potential at the right trigger output / blocks the passage of the next frequency pulse / t through the AND 3 circuit.

The circuit thus returns to the initial state, and the negative (executive) front of the output command Lt is removed from its left output.

In order to improve the operation of the device in the second variant, let us indicate only that with the arrival of the command L, the trigger J through the scheme

“OR 6 supports at the right entrance of memory trigger 7 a potential of“ 1. By virtue of this, the command B, prior to the completion of the formation of the output command Lt, will overturn trigger 2, but it does not affect the trigger of type 7. After the formation of the output command Lt is completed, and therefore the trigger / set to the state at the output of the circuit, “OR 6 will become zero and will override the memory trigger 7.

At the same time, potential “1” is applied to both control inputs of the “AND 4” circuit. The impulse frequency / t through the circuit "And 4 is fed to the right input of the trigger 2, forming a negative (performing) front

Commands B. The circuit returns to its original pending state.

In case the A commands B come to the device inputs simultaneously, the control inputs of the And 3 and 4 circuits receive a resolving positive potential 1 from the corresponding outputs of the flip-flops 1 and 2. The odio potential change at the inputs of the trigger 7 of the memory will not occur and they will remain in this state. Pulse

clock frequency f will go to the trigger input / or 2, and consequently, an Lt or W command will be generated depending on which input of the AND circuit (3 or 4) is the enable signal from one of the trigger outputs of type 7. Second output the team will be formed at the end of the formation of the first.

Subject invention

A synchronizer of two commands containing two triggers, a single input of the first of which is connected to the first AND circuit, and a zero input to the first synchronizer input, one input of the second trigger is connected to the second synchronizer input, and a zero input to the second And circuit, The first inputs of the "AND" circuits are associated with the third input of the synchronizer, and the second with the zero and single outputs of the respective triggers, characterized in that, in order to expand its functionality, it contains two circuits "OR and a memory trigger, whose inputs are connected cheny two schemes "OR, and outputs to the third inputs of respective circuits" And, the first circuit input "OR unit connected to outputs of flip-flops, a second input circuit" OR - zero outputs of these flip-flops.