SU369701A1 - ANALOG-DIGITAL CONVERTER - Google Patents

Description

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The invention relates to a digital electrical measuring technique and can be used in voltage converters with an IB code.

According to the main author. ov No. 226970 is a known analog-to-pin converter with automatic quantization of the measured voltage Ux in time with simultaneous amplitude quantization.

In such a converter, the error of its reproduction does not exceed a predetermined value with a certain probability, and the autocorrelation function of the measured voltage is determined.

The peculiarity of this converter is that the analog-code converter, based on the principle of counterbalancing the measured voltage I, is connected to a control unit, and a series of reference voltages С / о connect a counter, a reversible counter and a logic node, which is connected to the OUTPUT a digital-to-analog converter or to the input of a comparator device of additional exemplary voltages of both + At / o signs. As a result of measuring the voltage Ux, determining its magnitude over time T and comparing This increment is the absolute value | At / o | the device uses the autocorrelation function of the measured voltage Them to determine the interval

quantization T and quantization interval to determine the correlation function of the measured voltage Ux.

The quantization interval T is obtained on a revolving counter and in the event of overflow after the day is reset to zero, and in the case of decreasing the code of the reversible counter to zero at the next counting pulse, it becomes equal to the maximum value.

This is one of the drawbacks of the known circuit (Analog-to-code converter.

In order to expand functionality and increase reliability

in (the proposed converter additionally introduced a reversible counter of the multiplier, a coincidence circuit. maximum and minimum numbers, logic circuits for recording zero and full scale, and separate inputs

the latter and the second input of the logical intermediate reset are connected to the reversible counter of the multiplier through the coincidence circuits of the maximum and minimum number, and the other inputs are connected to the reversible

the interval counter, the entry for recording the full scale of which and the entry for recording the full scale of the multiplier counter are connected to the output of the logic circuit for recording the full scale. The drawing is a functional diagram

the proposed device.

The proposed device works as follows.

Under the acceleration of the signal "accelerated digit converter / measures the input signal Ux. According to (operator of Ux measurement from the driver / interval counter 2, the rewrite signal of its code is sent to counter 3, to which clock impulses are started to arrive from the converter / through the divider 4. Thus, the quantization interval of the input satellite Uy is formed.

Then, in the converter / is determined by the rotation of the input signal. In accordance with 31 increments, it connects or -Uo to the previously measured signal value, and the sum Ho + Ai / o or the difference Uo - Dyo is compared with the current value of the measured signal EhV, depending on this comparison is added or removed. per unit code of the reversible counter 2 interval (changes the quantization interval). For stationary random pragma npK6o; p determines automatically the rational values of the time intervals of quantization, which fluctuate on the reversible counter 2 intervals.

The reverse counter 2 is connected to the input of the reverse counter 5 of the multiplier, the latter through the decoder 6 controls the division ratio of divider 4. When the division ratio of divider 4 changes, the frequency applied to counter 3 changes, resulting in a change in the scale at which the int € (quantization break. The count of the quantization interval is taken from peBepc B Horo counter 2 intervals in the form of a binary code and divider 4, determining the multiplier code and thus the measurement threshold.

Suppose that the reversible counters 2 and 5 of the interval and the multiplier, respectively, are included in addition, and the code on them became maximal. On the next addition pulse, the max-number condominium scheme 7 and the full-scale record logic circuit 8 are activated, which again record the maximum code value in the equalizer interval .2 and 5 interval and multiplier. This process can be repeated many times. In this way, false readings of the values of the quantization interval during overflow of reversible counters are eliminated.

When turning on the reverse meters 2 and 5 on the Addition, provided that the readings of the reverse meters do not reach the maximum 31 values, the scheme works as follows.

Suppose that when the code of the reversible counter 5 of the multiplier per unit changes, the division factor of the clock pulses changes K times (in the particular case of K 2).

On the reversible-counter 2 interval, the code value increases to the maximum, -after the head, a unit is recorded in the reverse counter 5 of the Multiplier, i.e. the multiplier changes (switches the adedel), the intermediate reset logic circuit 9 is triggered, and in the reverse counter 2 of the interval. rewrites the code value reduced K times, and the frequency at the output of divider 4 decreases K times. Thus, with an increase in the interval (addition), the circuit operates at all intermediate code values on reversible counters 2 and 5

and multiplier.

However, if the code on the reversible counter 5 multiplier is equal to the maximum value in the reversible counter of interval 2, the code value is not overwritten, the reduced

-in K times, and the readings on it increase to the maximum value, yoka both reverse meters do not overflow. Then, the maximum values in both reverse meters will be overwritten.

So, for all intermediate values of the reversible counter code 5 multiplier, except the maximum, in addition mode, as the interval increases, the unit is written to the reversible counter 5 multiplier,

and in the reversible counter of the interval 2, the code value is rewritten, which is reduced K times by the multiplier value.

Suppose that reversible counters 2 and 5 of the interval and multiplier are included in

subtraction (the quantization interval is reduced) and the code on them became minimal.

On the next subtraction pulse, the minimum number 10 coincidence circuit is triggered and the logic circuit 11 takes up the zeros, which again writes the minimum (zero) code value into the reversible counters 2 and 5 of the interval and the multiplier. This process can be repeated many times. In this way, false readings of the values of the vdvanting interval are eliminated when releasing reverse meters to zero.

When turning on reversible counters 2 and 5 for subtraction, if the readings of reversible-counters have not reached the minimum values, the work of the -scheme occurs in the following way.

On the reversible counter 2 interval, the code value is reduced from the maximum value to the value smaller

IB scale K-times. As soon as the reading of the interval counter 2 interval reaches this value, with the arrival of the next Subdivision pulse, the logic circuit 8 is triggered by the full scale, which will trigger the maximum code value in the reverse counter 2 interval, and one is subtracted from the reverse counter 5 multiplier. In this case, the frequency of the pulses at the output of the divider 4 will increase K-times. Thus, when subtracting, the scheme works with all intermediate code values on the reversible counters 2 and 5 of the interval and multiplier.

As soon as the code on the reversible counter 5

the multiplier will become equal to the min. minimum value in the reversive counter of interval 2

the maximum value of the code with the feed of pulses to the subtraction is not overwritten, and when reaching zero T1, myo-yurat is overwritten by the iB zeros of both reversible counters.

Thus, the scale of the change in the quantization interval changes as it increases and 1 decreases as it depends on the measured signal.

The subject of the invention and

Analog-digital converter avh. St. No. 226970, characterized in that, in order to expand the functionality

ii improve the reliability, in addition, a reversible counter of the multiplier, a scheme of coincidence of the maximum and maximum numbers, logic circuits for recording zero and full scale, / and separate inputs of the latter and the second input of the logic circuit (Intermediate reset of the connection 1y with the reversible multiplier of the multiplier through the coincidence schemes of the maximum and minimum numbers, and the other inputs are connected to the reversible counter of the interval, the record of which is written in the full scale of which is n the input of the record of the full scale of the counter cpol connected to the output of the logical scale record of the Lola scale.