SU1307442A1 - Device for determining time position of signal - Google Patents

Abstract

The invention relates to a pulse technique and can be used in measuring and automated signal processing systems. The purpose of the invention is to expand the functionality. To achieve this goal, triggers 5 and 16 are entered into the device / 8, register 15, AND-OR elements 8, 9, switch 7, driver 12. The device also contains a counter 1, 17, analog-to-digital converter 2, a discriminator 3 level , memory block 4, triggers II and 14, And element 13, input 18 and output 19 tires, generator 6, comparator 10. The device ensures the high accuracy of determining the temporal position of signals of various shapes, which makes it possible to measure the absolute maximum of the signal and time - variable about labels in the form of a pulse with a fixed delay relative to the time the SS signal reaching a level equal to half the maximum value. 2 Il. (L os about 4 4i

Description

The invention relates to a pulse technique and can be used in measuring and automated signal processing systems.

 The purpose of the invention is to expand the functionality of the device.

Figure 1 shows the functional diagram of the device; figure 2 - timing charts of his work. ,

The device contains the first counter 1, analog-to-digital converter (A1SCH) 2, discriminator level 3, memory block A, trigger 5, generator 6, switch 7, AND-OR elements 8 and 9, comparator 10, trigger P, driver 12, element 13, trigger 1A, register 15, trigger 16, counter 17, as well as input 18 and output 19 tires. The device input bus 18 is connected to the input of the discriminator 3 and the analog input of the BP 2, the output of which is connected to the information input of the memory 4, the first input of the switch 7 and the information input of the register 15, the output of which is connected to the first input A of the comparator 10, the second input Which is connected to the output of switch 7, the second and third inputs of which are connected to the output of memory block 4, whose address input is connected to the output of the first counter 1, the counting input of which is connected to the output of the first element AND-OR 8, the first input of which th is connected to the input for setting resolution in one of the first flip-flop 11, the lane

control input of the switch 7, control inputs of the memory block 4 and. The first counter 1, the direct output of the third trigger 5 and the first input of the second element AND-OR 9, the second input of which is connected to the second input of the first element AND-OR 8 and the first output of the generator 6, the second output of which is connected to the clock input A1SCH 2 and third the inputs of the second 9 and first 8 elements IGM, the fourth input of the latter is connected to the control input of the register 15 and the inverse output of the third trigger 5, the installation input in O which is connected to the installation input in O of the fourth trigger 16 and the output of the element And 13, the second. whose entrance by It is connected to the output of Comparator 10, and the first is connected to the second input of the

o

f5

about 25 30

35

40

45

switch 7 and the direct output of the first trigger 11, the installation input in which t is connected to the output is equal to the comparator 10, and the installation input in O is connected to the inverse output of the fourth trigger 16, the installation input in 1 which is connected to the clock input of the register .15 and input Less than the comparator 10, and the direct output of the fourth trigger 16 is connected to the control input of the driver 12, the output of which is connected to the installation input 1 of the third trigger 5 and the zero input of the second counter 17, the counting code of which is connected to the output of the second el The control input is connected to the forward output of the second trigger 14, the installation input of which is connected to the inverse clock input of the driver 12 and the output of the discriminator 3, and the installation input to O is connected to the overflow output of the second counter 17, register zeroing input 15 and the output bus 19 of the device, and the fourth input of the second element-OR 9 is connected to the bus of a single voltage level,

The control inputs of the memory block 4 and the first counter 1, connected to the direct output of the trigger .5, provide the direct counting mode in the counter 1 and the recording mode information from output A1SCH 2 in the memory block 4 and the subtraction modes in the zero state of this trigger. and read the shans respectively in the counter 1 and memory block 4 at a single voltage level at the output of the trigger 5,

The first 1 and second 2 control inputs of the switch 7, connected respectively to the first outputs of the flip-flops 5 and 1 1, provide for the transmission of codes from the first B1, second B2 and third EI information inputs of the switch 7 to its output in accordance with the truth table.

3

The control input of register 15, which is connected to the inverse output of trigger 5, provides for recording information to the register at a single voltage level at the trigger output. The counting mode by the counter 17 is carried out when a single level control is fed to its input from the direct output of the trigger 14.

The A / D converters 2, register 15, and memory block 4 have parallel output codes of n bits each, and switch 7 and comparator 10 are (n + 1) digit elements, with the most significant bits of the first and second bits and the least significant bits of the information inputs. the switch 7, as well as the most senior bit of the input input A of the comparator 10 are connected to a logical zero circuit.

The outputs of the ADC 2 are connected to the p younger - 20 output signal Less from the computer

We will discharge the first information input of the switch 7, the outputs of memory block 4 will be assigned to the junior bits of the second and n star0; they will have the third information inputs of the switch 7, and the outputs of register 15 will be connected to the junior bits of the first input of the comparator 10.

The device works as follows

In the initial state, all the triggers, the register and the second counter are in the zero state (initial reset circuits are not shown),

Before the occurrence of a signal that exceeds the detection threshold, the second trigger 14 is in the zero state. It prohibits the operation of the second counter J7 on the control input. A / D converter 2 converts the analog signal fed to the input bus 18 with a sampling frequency f, defined by the second generator output 6, into a code.

The generator 6 provides for the formation of two sequences of non-overlapping pulses, with the frequency of the pulses at the first output of the generator being k times higher than the frequency at the second output.

In the zero state of the third trigger 5, the AND-OR 8 element at the synchronization input of the first counter 1 receives pulses from the second output of the generator 6. The first counter 1 generates successively increasing addresses, which, in block 4 of the memory, write the codes from the output of the ADC 2, At this after overflow lane

First counter 1, new codes with A1DP 2 are recorded in memory block 4 of the zero address, replacing the previously recorded information. The level of the logical unit - from the inverse output of the third trigger 5, acting at the control input V of the register 15, allows writing the codes arriving at its information input D from the output of APP 2 according to the synchronization pulses generated by the comparator 10 at its output Less in those cases when the code value in register 15 is less than the code value at the output of the A / D converter 2, - Thus, in register 15 the maximum code value obtained over the entire time from the beginning of the analyzed interval is stored. Simultaneously with recording the new code value in register 15

five

0

AC g

35

0

0

The rator 10 is set to install the fourth trigger 16 into a single state. The indicated state of the device is maintained until time t (Fig. 2), when the signal exceeds the detection threshold level and the discriminator of the 3 level switches to one state.

The output signal of the discriminator 3 level sets the second trigger 14, which allows the second counter 17 to work, to the counting input of which at zero state of the third trigger 5, the signals from the second output AND-OR 9 only come from the second output of the generator and 6 low frequency, which determine the sampling period of the input signal of the A / D converter 2 and the frequency of access to block 4 memory when writing codes in it in real time.

At the point of decay of the first half-wave of the signal at time t, discriminator 3 is turned off, fourth trigger 16 is in one state, allowing control input V to enable generator 12, which is triggered on the falling edge of the discriminator 3 level, generating a reset pulse of the second counter 17 and setting 1 third trigger 5.

The logical unit from the forward output of the third trigger 5 switches the first counter 1 to the subtraction mode, the memory block 4 to the information reading mode and the switch 7 to the transfer mode of the codes from the memory block 4 to the second input of the comparator 10, Simultaneously to the input of the first counter I, through the first element, AND-NE 8, begins to receive from the first output of the generator b high frequency signals, which are used to perform an accelerated reading from memory block 4 in the reverse order

Since the amplitude code of the first half-wave of the signal is stored in register 15 and this code was previously recorded in memory block 4, when reading, the information comes the sampling moment from memory block 4 of the specified code, while the output Equals Comparator 10 produces a signal at the single input of the first trigger 11J, the installation condition of which in the single state at the time under consideration is complete I (since the logical unit signal from the direct output of the third trigger 5 acts on the installation enable input and the input R goes to the reset input After the first trigger 11 is set to one, a combination of signals V, -V., n is formed at the output of comparator 7, which is doubled. (due to the shift to the left) the value of the code from its third information input connected to the output of memory block 4. At the output of the Less Comparator 10, a signal is again generated due to the fact that the value of the maximum code stored in register 15 is small duplicated code values recorded in the memory unit 4 immediately before the maximum recording code.

However, the occurrence of these signals at the output Less than comp. 10 does not change the state of the device, in particular, change the code in register 15, because the input to the write enable V of register 15 receives a logical signal. information from memory block 4,

At the instant tj at the output. More than the comparator 10, a signal is generated indicating that the double value of the code read from memory block 4 has become less than the amplitude value code and, therefore, when sampling from memory block 4, the codes corresponding to

0 5 0

Q

five

five

The first half-wave of the signal reached a point with a level close to half the amplitude. The impulse from the output of the Comparator 10 goes through the element I 13 to the input of the installation of the third 5 and fourth 16 flip-flops. .

During the time interval from the moment t to tj, while the trigger 5 is in the unit state, the counting input of the second counter 17 through the second element AND-OR 9 from the first output of the generator 6 receives high-frequency pulses, in the intervals between which through the third input the second element 9 receives low frequency pulses from the second generator output 6; Summing these two sequences of pulses provides in the second counter 17 at time t "a time code equivalent to the code that would be in it if The impulse would only receive pulses from the second output of the generator 6 during the interval from the moment of the signal under test on the bus 18 of the device of level 9 of different half of the amplitude value (t) to the moment t j.

From the moment -j; the third trigger 5 is in the zero state and the second counter 17 continues encoding the current time interval from the moment tg on signals from the second output of the generator 6 in real time. When the second half-wave signal of the detection threshold is crossed, the level 3 discriminator again switches into a single state that does not lead, however, to change the device sos to t, when the signal level on the device bus 8 begins to exceed the amplitude level of the first half-wave whose code is stored in register 15,

From the moment t, the output signals MeHBDje from the com. Parator 10 trigger 16 is again set to one State, and the register 15 begins to write the codes from the A / D converter 2 until the amplitude code of the second extremum is obtained.

At time tj, the discriminator 3-level is turned off, shaper 12 generates a pulse, nulling the contents of the second counter 17, and sets the third trigger 5 to one state, providing a measurement of the beginning of the second extremum similarly to that described for the first half-wave of the input signal. Despite the fact that the third half-wave of the signal crosses the detection threshold before the measurement at the second extremum ends, the measurement process of the latter is not interrupted (trigger 5 remains in the unit state until the end of the measurement)

At time tg, the signal on bus 18 reaches a level equal to half the absolute maximum of the signal. The code of this level, like the codes of the preceding and subsequent samples, is recorded in memory block 4 and time intervals when trigger 5 is in the zero state. At time t, the second counter 17 is zeroed for the third time and from memory block 4 begins to read codes in reverse order until the code recorded at time tg is read. By time tg, a counter proportional to the time interval from the time t to tg is set in counter 17. After the third trigger 5 is set in O at the moment to counter 17 only impulses come from the second output for generators 6 and the counter 17 is measured in real time the time interval from the instant tg, fourth extremum in the signal exceeding the threshold, the device is not sensed since the register 15 is stored an absolute maximum code, and the comparator 10 generates no output signal less.

After a time interval,

equal to 1, from the moment i the second counter 17 overflows and the signal is transferred. From its output, the SA enters the device bus 19 in the form of a time stamp delayed by a fixed interval 1 with respect to the moment when the signal reaches a level equal to half the amplitude of the absolute maximum. The same signal sets up the initial register 15 and the second trigger 14, preparing the device for receiving the next signal. The value of Bj) eMeHHoro interval T is chosen

five

0

five

ABOUT

five

0

five

0

five

from the condition of a guaranteed fall in the amplitude of the signal on the device т 18, below the detection threshold by the time the second counter overflows 17.

The device achieves the high accuracy of determining the time position of signals of various shapes, which allows it to expand its area of use by measuring the absolute maximum of the signal and forming a time stamp in the form of a pulse with a fixed delay relative to the time the signal reaches half the maximum value.

Claims (1)

Invention Formula A device for determining the temporal position of a signal, containing an analog-to-digital converter, two counters, first and second triggers, a memory block, a comparator, an AND element, a generator and a level discriminator whose input is connected to the input of the device and to the analogue analogue digital input converter, the output of which is connected. To the information input of the memory block, the address input of which is connected to the output of the first counter, the control input of which is connected to the control input of the memory block, output Equal to the comparator plug The output of the discriminator of the level is connected to the input of the installation of 1 second trigger, the output of which is connected to the control input of the second counter whose output is the output of the device that, in order to expand the functionality, the third and fourth triggers, the register, the first and second AND-OR elements, the switch and the driver, the output of which is connected to the reset input of the second counter and to the installation input in the single state of the third trigger, the direct output of which is connected to the control input of the first counter, the first control input of the switch, the first inputs of the first and second AND-OR elements, and the enable input of the first trigger setting to single state, the output of which is connected to the second control input of the switch, the first information input of which is connected to the output of the analog-digital converter and to the information input of the register, to which the input is connected to the first input of the comparator. the second input of which is connected to the switch output, the second and third information inputs of which are connected respectively to the output of the memory unit directly and shifted one bit to the left, the reset input of the first trigger is connected to the inverse output of the fourth trigger, whose direct output is connected to controlled input of the driver, the synchronization input of which is connected to the output of the level discriminator, the first output of the generator is connected to the second inputs of the first and second I-1-SHI elements (the third inputs of which are combined and connected us to the second output the generator and the analog-digital converter synchronization input, the synchronization input of the first counter is connected to the output of the first AND-OR element, the fourth input of which is connected to the inverse output of the third trigger and to the register recording enable input, the synchronization input of which is connected to the installation input .the fourth trigger, and with the output Less than the comparator, the output of which is more connected to the second input of the element I, the output of which is connected to the reset inputs of the third and fourth triggers, the fourth input second AND-OR connected to the mud layer logical unit, register and reset inputs of the second flip-flop connected to the output of the second counter whose clock input connected to the output of second AND-OR. tOin2i3 t tSt Editor A. Ogar Compiled by I. Shishkin Tehred And „Popovich Corrector S. Cherni Order 1630/48 Circulation 371 Subscription VNIIII State Committee € 00 for inventions and discoveries N3035, Moscow, Zh-35, .Raushska nab., d.4 / 5 Production and printing company Uzhgorod, st. Project, 4