SU1559327A1 - Device for measuring distortions of pulse duration - Google Patents

Abstract

The invention relates to a measurement technique and can be used in devices for determining distortion of a telegraph signal. The aim of the invention is to extend the functionality by searching for the maximum distortion of the pulse duration. The goal is achieved by introducing into the device for measuring the distortion of the pulse duration of the elements And 6.7, triggers 8.11, the element ZI-ZI-OR 10 and the reverse shift register 9. The device also contains a driver 1, a reference frequency generator 2, an AND 3 element, a trigger 4, a frequency divider 5, a code comparison block 13, a memory block 13, an indicator 14, a counter 15, and an input bus 16. 4 Il.

Description

The invention relates to a measuring technique and can be used in automated systems to determine the maximum distortion of pulse durations in a series of telegraph packets.

The purpose of the invention is to increase the accuracy of measurement of the distortion of the pulse duration.

Figure 1 shows the block diagram of the device; figure 2 - the timing diagram of his work} on fig.Z - diagram of the driver; 4 shows block comparison circuit diagrams.

The device contains a shaper 1, a generator 2 of the reference frequency, element 3, trigger 4, frequency divider 5, elements 6 and 7, trigger 8, reversing shift register 9, element ZI-ZI-ILY 10, trigger 11, block 12. comparison codes, memory block 13, indicator 14, counter 15 and input bus 16.

The input bus 16 is connected to the first input of the shaper I, and the output of the reference frequency generator 2 is connected to the first input of the IZ element, the second input of which is connected to the forward output of the trigger 4, and the output is connected to the input of the frequency divider 5. The first and second groups of information outputs of the memory unit 13 are connected respectively to the first and second group of information inputs of the code comparison unit 12 and the indicator input.

The output of the generator 2 of the reference frequency is connected to the second input of the imaging unit 1, the first output of which is connected to the single input of the trigger 4, the zeroing input of the frequency divider 5, the first single input of the trigger 8, the single input of the trigger 11 and the offset shift register 9.

The second output of the imaging unit 1 is connected to the zero input of the trigger 4, the polling inputs of the code comparison unit 12 and the memory block 13, and the counting input of the counter 35, the output connected to the zero input of the memory 13, the information inputs of which are connected to the information output group and the first and second outputs of the comparison result of the code comparison unit 12, the third group of information inputs of which are connected to the information outputs of the reverse shift register 9, the outputs of the first and nth bits of which are connected to the first inputs respectively per-

first and second elements AND element ZI-ZI-OR 10, the second inputs of which are combined and connected to the clock input of the reverse register 9 shift and the output element And 6, the first input

which is connected to the output of the frequency divider 5 and the first input of the And 7 element, and the second input of the And 6 element is connected to the forward output of the trigger 8, the second single input of which is connected to the clock input of the trigger 11 and the output of the And 7 element, the second input of which is connected to the inverse of the trigger output 8, the zero input of which is connected to the output of the element ZI-ZI-OR

0 10 with the third input of the second element AND element ZI-ZI-OR 10 connected to the control input of the reverse shift register 9 and the forward output of the trigger 11, the inverse output of which is connected to the third input of the first element AND element ZI-ZI-OR 10 and input mode selection block 12 comparison codes.

Comparison unit 12 codes (figure 4)

0 contains a code converter 17, a digital comparator 18, three groups of information inputs, a group of information outputs, a mode selection input, a polling input and two output outputs

5 comparisons.

The first and second groups of information inputs are connected respectively to the first and second groups of information inputs of the digital comparator 18, the third group of information / inputs of which are connected to the group of information outputs of the code comparison unit 12 and the information output of the code converter 17, the information inputs of which are connected to the third group information inputs of the code comparison unit whose polling input is connected to the clock input of the code converter 17, and the mode selection input is connected to the direct and inverse m digital input mode selection comparator 18, first and second comparison result outputs of which are connected respectively to the first and second outputs result sravne0

five

no codes.

The former (FIG. 3) contains a low-frequency filter 19, a limiting amplifier 20, a shift register 21,

five

and 23,

one

two elements And 22 and 23, the first and second inputs and the first and second outputs.

The first input of the imaging device is connected to the input of the low-frequency filter 19, the output of which through the amplifier-limiter 20 is connected to the information input of the shift register 21, the clock input of which is connected to the second input of the imaging device and the first inputs of the And 22 and 23 elements.

The first output of the shift register 21 is connected to the second input of the And 23 element directly and to the second inverse input of the And 22 element, and the second output of the register is connected to the third input of the And 22 element directly and to the third inverse of the And 23 element, and the outputs of the And 22 elements and 23 are connected respectively to the second and first outputs of the imager.

The device works as follows.

In the initial state, the trigger 4, the counter 15, and the memory block 13 are reset. The input signal (Fig. 2a) is fed to the first input of the imager ls to the second input of which pulses are output from the output of the reference frequency generator 2,

Shaper 1 eliminates crushing and impulse noise of the input signal, temporarily assigns the pulses of the input signal to the pulses of the reference frequency generator which are much shorter than the duration of the input signal and form the pulses corresponding to the front and rear edges of the input signal.

The input signal is fed to the input of the low-frequency filter 19, which eliminates the splitting of the input signal and impulse noise affecting the input signal.

In the limiting amplifier 20, the output signal of the filter 19 is converted into square normal-level pulses, which are fed to the information input of the shift register 21, made in the form of a two-bit register, and advanced along its bits under the action of the oscillator pulses 2 of the reference frequency at its clock input.

At the output of the element And 23 pulses are formed, corresponding to

1559327

0

0

five

the front of the input signal (Fig.26), and the output of the element And 22 - the rear - the front (figv).

The pulses corresponding to the leading edge-inlet signal switch the triggers 4, 8, and 11 into one state and reset the frequency divider 5 and the reverse shift register 9 to the initial state.

Moreover, all bits of the frequency divider 5 and the reverse shift register 9 are set to the zero state, except for the first bit of the reverse shift register 9, which is set to one state.

The output signal of the trigger 4 (FNG.2g) unlocks the element I 3, allowing the passage of pulses from the output of the reference frequency generator 2 to the input of the frequency divider 5, from whose output the pulses through the element 6 unlocked by the direct output of the trigger 8 reverse shift register 9. In this case, the division factor of the frequency divider 5 is chosen such that the ratio

thirty

TO

JЈP-

2n

five

where K is the frequency division factor; / about

 OP

the duration of the elementary parcel of the input signal; the frequency of the output voltage of the generator 2 reference frequency, and

1 / f

on

  Sl

P

number of reversing bits

register 9 shift. The maximum distortions of the duration of the input pulses measured by the device are + 50%. So, for example, if the duration of the input signal

Ј;

1,5С

about

then the device will record distortion by + 50%. If the duration of the input

signal

"; 1, 51

 about

then the device will assign such a dressing to a discharge of two-fold in duration and will detect a distortion of -49%. The width of the shift register 9 is selected so that one sampling quantization of the input signal duration corresponds to a 1% distortion of the sending duration, since the maximum distortions of graphic signal telephones should not exceed + 50%. Otherwise, the signal is related to a different length bit. For example, when receiving a double parcel, the distortion of which reaches 51% (and higher), i.e.

B

, 5 s-0 or s; 2.5 and 0

In the first case, the device will assign the received parcel to the one-time bit and record the result of the distortion

+ /

L

t-o

L.

with/,

-ten

Bg

/100%,

and in the second case, the received dressing will be referred to the threefold discharge and the result of the distortion will be recorded

15

L l.

 L

100%.

When pulses arrive at the clock input of the reverse register 9

it 1 h

20

35

the shift of logical 1, recorded in the first bit, is shifted by register register bits (fig. d) in the forward direction, since its control input contains a logical unit signal coming from the direct output of the trigger 11 In this case, the logical unit in the nth digit of the reversible shift register 9 at the output of the ZI-ZI-OR 10 element forms a 0-second pulse that switches the trigger 8 to the zero state, which locks the AND 6 element and unlocks the AND 7 element. pulse from the output of the divider 5 frequency, through the unlocked element And 7 (fig.2e) y sets the trigger 8 again to the single state, and the trigger 11 switches to the zero state at the clock input, the forward and inverse outputs of which change the operating mode of the reverse shift register 9 to the reverse shift and switch the code comparison unit 12 to the parcel search mode from the minimum duration (i.e., with the maximum distortion of the negative sign), then during the n cycles of operation of the reverse shift register 9, the logical unit is advanced in its discharge in the direction from the highest bit to the lowest mu.

When a logical unit appears at the output of the first bit of the register, at the output of the ZI-ZI-OR 10, a signal is again generated that will switch the thrash 8 to the stupid state, which is c-1, p, 1-ny before the appearance of the impulse on the puff element And 7, which is 15593278

ry switches triggers 8 and 11 to one state.

In this case, the code comparison unit 12 will again return to the parcel search mode with the maximum duration (i.e., with the maximum distortion of the positive sign), and the operation mode of the reverse shift register 9 will be changed to the opposite one.

When the trailing edge of the input signal appears at the second output of shaper 1, a signal appears that switches trigger 4 to the zero state, prohibiting the passage of pulses from the output of the reference frequency generator 2 through element 3 to the input of frequency divider 5.

In addition, this signal allows the code comparison unit 12 to compare the number currently stored in memory block 13 with the number recorded in the reversing shift register 9, taking into account the sign of distortion, which determines the output signal of the trigger 11 and records the result of the comparison two numbers in memory block 13, erasing, if necessary, the previous measurement result. The result of the measurement of the amount of distortion stored in the memory unit 13 is displayed on the indicator 14.

The signal from the second output of the formulator 1 is fed to the input of the counter 15, the capacity of which determines the analysis base, i.e. number of measurements. The signal from the overflow output of the counter 15 sets the memory unit 13 to the initial state, and the measurement cycle is repeated.

The principle of operation of the code comparison unit 12 is as follows.

The output signals of each of the bits of the reverse shift register 9 are fed to the information inputs of a 1-n converter code 17, which converts an n-bit position code to m bit binary code at the moment the Polling signal is applied at the clock input of the converter.

The output codes of the converter arrive at group A of the information inputs of the digital comparator 18 and at the information inputs of the memory block 13. The groups of information inputs B and C of the digital comparator receive codes from the information PIRS of the memory block 13.

40

55

The memory unit 13 can be made in the form of two registers providing storage and rewriting of information.

Digital comparator 18 compares two numbers of the current value of a number characterizing the distortion of the input signal coming from converter code 17 (input A) with one of the numbers B or C, arriving at the inputs of the comparator from the information outputs of memory block 13, according to the principle L B or A C.

The specific comparison number is determined by the level of the signal coming from the inverse output of the trigger 11 to the mode selection input of the code comparison block 12 and characterizing the distortion sign of the device input signal.

At the moment of arrival of the Poll pulse (Fig 2b) from the output of the imaging unit 1, the memory block 13 can be in the initial (zero) state, and the output signal, for example, the fifth bit of the reverse shift register 9 (FIG. 2d), coincided with the signal Poll.

At the same time, at the output of the code converter 17, a code of the number corresponding to the positive distortion of the input signal + 5% is generated. (At the inverse output of the trigger 11 is set to a single level), In this case, the output AB of the digital comparator 18. As a result of the number A of the number B stored in block 13 of the memory being exceeded (in the initial state), an impulse corresponding to that the number received from the output of the converter 17 of the code (A) is greater than the positive number stored at the time in block 13 of the memory (B). When this signal is received simultaneously and the signal is polled at the information inputs of memory unit 13, the latter records the value of number A while simultaneously erasing the previous number B. If during further measurements of the input signal the value of the positive distortion is less than + 5%, i.e. . (A B), then the state of the memory block 13 remains unchanged, and its state can be changed only when the magnitude of the positive distortions

Jq

15 20

25 30

93271P

will exceed the value of + 5% (i.e. will be A B).

If the distortion of the input signal has a negative sign, then in digital comparator 18 the current value of the number A is compared with the number C stored in the memory block 13.

The algorithm for comparing numbers and searching for the quantity ./A/ / C / is similar to that described.

In block 12, code comparison compares two numbers and searches for a number corresponding to the maximum distortion of the input signal.

In this case, the maximum distortion with a negative sign corresponds to the minimum duration of the input signal, and the maximum distortion with a positive sign corresponds to the maximum duration of the input signal. The maximum distortion is determined with respect to the duration of the elementary parcel regardless of the multiplicity of the telegraph signal sent to the input of the device in accordance with the dependence

8 "% yo,

h °°

O - the value of the distortion of the parcel

at %.

Where

five

0

0

five

Introduction of the elements 6 and 7, triggers 8 and I, the element ZI-ZI-ShTI 10, the reverse shift register 9 and the corresponding execution of the code comparison unit 12 to the known device allows to measure the parcels of any multiplicity with distortions of any sign.

Claims (2)

1. Device for measuring pulse duration distortion, comprising a driver, a reference frequency generator, an element, a trigger, a frequency divider, a code comparison unit, a memory block, an indicator, a counter and an input bus connected to the first input of the driver, and the output of the reference frequency generator connected to the first input of the first element I, the second input of which is connected to the direct output of the first trigger, and the output connected to the input of the frequency divider, the first and second groups of information P1 the outputs of the memory block are connected to the first and second groups of information inputs of the code comparison block and the indicator input, characterized in that, in order to improve the accuracy of measuring the pulse length distortion, two triggers are added to it, two AND elements, ZI-ZI-OR element and a reverse shift register, with the output of the reference frequency generator connected to the second input of the imager, the first output of which is connected to the single input of the first trigger, the zero divider input of the frequency divider, the first single input of the second trigger, a single input of the third trigger, and an input of a reverse shift register; a second output of the driver forms a connection to the zero input of the first trigger; the polling inputs of the code comparison unit and the memory block; and the counter input of the counter, the output of which is connected to the memory zero reset input, the inputs of which are connected to the group of information outputs and the first and second outputs of the comparison result of the code comparison unit, the third group of information inputs of which are connected to the information outputs of the reverse the first shift register, the outputs of the first and n-th bits of which are connected to the first inputs of the first and second elements AND the ZI-ZI-OR element, respectively, the second inputs of which are combined and connected to the clock input of the reverse shift register and the output of the second element AND, the first input which is connected to the output of the frequency divider and the first input of the third element, and the second input of the second element I is connected to the forward output of the second trigger, the second single input of which 0 five 932 0 five 0 five 0 712 connected to the clock input of the third trigger and the output of the third element And, the second input of which is connected to the inverse output of the second trigger, the zero input of which is connected to the output of the element ZI-ZI-OR, the third input of the second element AND of the element ZI-ZI-OR connected to the control input of the reverse shift register and the direct output of the third trigger, the inverse output of which is connected to the third input of the first element AND of the ZI-ZI-OR element and the mode selection input of the code comparison block, 2. The device according to claim 15, wherein the code comparison unit comprises a code converter, a digital comparator, three information entry corpses, a group of information outputs, a mode selection input, a polling input and two outputs of the comparison results, the first and second groups of information inputs connected, respectively, to the first and second groups of information inputs of a digital comparator; a third group of information inputs of which is connected to a group of information outputs of a code comparison unit and information outputs; code generator, the information inputs of which are connected to the third group of information inputs of the code comparison unit, the polling input of which is connected to the clock input of the code converter, and the mode selection input is connected to the direct and inverse digital mode selection selection inputs, the first and second outputs of the comparison result of which connected, respectively, to the first and second outputs of the comparison result of the code comparison unit. Fig.Z