SU1742985A1 - Analog-to-digital amplitude detector - Google Patents

Abstract

The invention can be used in information processing devices. The detector contains an analog-to-digital converter 1, a memory register 2, a control pulse shaping unit 3 consisting of an analog comparator 4, a 5 clock pulse generator, a delay element 6, a pulse counter 7, a shift register 8, and a digital comparator 9. 1 Il.

Description

The invention relates to amplitude modulated pulse detection equipment and can be used in information processing devices.

The purpose of the invention is to improve the accuracy and noise immunity of detection.

The drawing shows a structural electrical circuit of an analog-digital amplitude detector.

The analog-to-digital amplitude detector contains an analog-to-digital converter (ADC) 1, memory register 2, and a control pulse shaping unit 3 consisting of an analog comparator 4, a clock generator 5, a delay element 6, a pulse counter 7, a shift register 8, and digital comparator 9.

Analog-digital amplitude detector works as follows.

Input signal - amplitude modulated pulses fed to the input

The A / D converter 1 and the first input of the analog comparator 4. The A / D converter 1 continuously converts the input signal into a digital binary code with a conversion frequency equal to the generator frequency of 5 clock pulses. Writing the code values from the outputs of the A / D converter 1 into the memory register 2 is carried out only of those that correspond to the instants of time for converting the pulse amplitude approximately in the middle of its duration. The signal in the middle of the pulse is sampled using block 3 as follows. When the signal level exceeds the threshold level, set a priori by the noise level and set as a constant voltage at the second input of the analog comparator 4, the latter is triggered and starts the pulse counter 7. Counter 7 starts counting the number of pulses from the output of the generator 5. On the falling edge of the input pulse, analog comparator 4 returns to the outcome (L

WITH

vi

N

GO

Yu

00

cl

In this position, the counter 7 stops counting pulses, the number of which, expressed in a digital binary code, is halved by shifting one bit to the left using the shift register 8 and stored in register 8 until the next input pulse arrives and expires. Then, after a time determined by the delay value of the delay element 6 and equal to the recording time of the signal code in the register 8, the counter 7 is zeroed. When the second (next) pulse arrives at the input of the analog-digital amplitude detector, the process described above is repeated, but during the pulse counting by the pulse counter 7, the magnitude of the linearly increasing code value at the outputs of the counter 7 is compared with the code stored in register 8. At the moment of time when the value of code A from the output of counter 7 is equal to or becomes larger than the value of code B, the digital comparator 9 will be activated. At its output, the front of the pulse is formed, which is used to record the amplitude of the input signal. th pulse in its middle duration in the register 2 memory. The value of code B is proportional to half the duration of the previous pulse. When changing the shift value in register 8 or using a decoder with a memory register instead, the location of the sampling pulse relative to the beginning

the input pulse can be changed to achieve the minimum detection error.

Claims (1)

Analog-to-digital amplitude detector comprising an analog-to-digital converter and a memory register connected in series and connected between the input and output bus, as well as an analog comparator, the first input of which is connected to the input of an analog-to-digital converter, and a clock pulse generator differing from that, in order to increase accuracy and noise immunity, a delay element, a shift register, a digital comparator and a pulse counter, whose counting input is connected to the clock one, are introduced into it the analog-digital converter and the clock generator output, the control input — with the input of the delay element, the control input of the shift register and the output of the analog comparator, the reset input — with the output of the delay element, and the outputs with the inputs of the shift register and the first inputs of the digital comparator, the second inputs of which are connected to the outputs of the shift register, the output to the memory register control input, and the second input of the analog comparator are connected to the reference voltage bus.