SU1599892A1 - Device for recording/playback of analog signals - Google Patents

Abstract

The invention relates to the accumulation of information and can be used for recording and reproducing analog signals. The purpose of the invention is to reduce the sampling error in the recording-reproduction process. In the recording mode, the first pulse of the frequency divider 12 is fed to the analog-to-digital converter 1, which starts the first conversion cycle of the output analog signal, and on the counter 4, which forms the address of the first line in memory block 3. At the same time, a binary code is generated at the data outputs of the analog-digital converter 1, corresponding to the value of the input analog signal in the first conversion cycle. This binary code is written in the first line of the memory block 3. Similarly, binary codes corresponding to the values of the input signal in subsequent conversion cycles are written to the other lines of the memory block 3. In the recording mode of the readiness pulses of the analog-digital converter 1, the binary codes contained in the rows of memory block 3 are sent to its outputs. By readiness pulses, these codes are written to register 9, from the outputs of which they are fed to digital-to-analog converter 5. At the same time, digital-analog converter 5 outputs discrete analog signal values to the output bus 6 proportional to the analog input signal values in conversion cycles.

Description

The invention relates to the accumulation of information, and specifically to devices for recording and reproducing analog signals.

The purpose of the invention is to reduce the sampling error in the recording-reproduction process.

The drawing shows one of the possible variants of the proposed device for recording and reproducing analog signals.

The device contains an analog-to-digital converter 1 connected by an analog input to an input bus 2 of an analog signal, connected by data outputs and data readiness output respectively to information inputs and a reverse input of memory block 3 and connected by address inputs with outputs 4, digital to analog. a converter 5 connected by an output to the output bus 6, and an input bus 7 of the clock signal. In this case, the input bus 7 of the clock signal can be connected to the output of the generator 8 of the clock signal.

The device also contains a register 9 connected by outputs to the information inputs of the digital-to-analog converter 5, connected by a reset input and a recording input, respectively, to the input bus 10 of the installation and to the readiness output of data from analog-digital converter 1 and connected by information inputs to the outputs of memory block 3 equipped with a connected with its mode select input with input bus 11 modes, and a divider of 12 frequencies. Frequency divider 12 is connected by a counting input to the input bus 7 of the clock signal and is connected to the counting input of counter 4 and to the quenching and converting input of the GO-1SChA converter 1. The analog-pF converter 1 is equipped with an input bus 13 connected to its reference voltage input a reference voltage connected to the input voltage of the reference 1-voltage analog-to-analog converter 5. At the same time, the input input 10 of the installation is connected to the reset inputs of the counter 4 and the frequency divider 12,

The proposed recorder-playback analog signals works as follows.

About Q

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In the write mode on the input bus 11 of the mode, the logical unit level is applied to the mode select input of the memory block 3. At the same time, after setting the logical zero level on the bus 10 of the setup, the first pulse of the pulse sequence from the output of the frequency divider 12 is fed to the blanking and conversion input of the analog-to-digital converter 1, which starts the first 1 conversion of the analog signal fed through the input bus 2 of the analog signal. The first pulse of the pulse sequence from the output of the frequency divider 12 also enters the counting input of counter 4, which forms the address of the first row in block 3 of the memory. After a conversion time interval, the outputs of analog-to-digital converter 1 produce a binary code corresponding to the value of the input analog signal during the first conversion cycle. At the same time, at the readiness output of data from the analog-digital converter 1, the leading edge of the data readiness pulse is formed, with which the binary code from its data outputs is written into the first line of the memory block 3. After the data readiness pulse completes, the counter 4, via the second pulse of the pulse sequence from the output of the frequency divider 12, generates the address of the second row in the memory block 3. In this case, in the analog-to-digital converter 1, the second analog signal conversion cycle starts. At the outputs of the analog-to-digital converter 1, a binary code is generated corresponding to the value of the input analog signal during the second conversion cycle. This binary code is written in the second line of the memory block 3. Thereafter, binary codes are written in the same way. Corresponding to the values of the input analog signal on the subsequent conversion cycles, in the subsequent lines of the memory block 3. The recording mode is terminated when the level of logical unity is received. on the input bus 10 installation,

Claims (1)

In the read mode of the input mode bus 11, the mode selection input of the memory block 3 is supplied. A logic zero level is applied. At the same time, after setting the logic zero level on the installation input 10, the first pulse of the pulse sequence from the output of the frequency divider 12 is fed to the blanking and conversion of analog-to-digital converter 1 and to the counting input of the counter 4, which forms the address of the first line in memory block 3. Analog-to-digital converter 1 generates a data readiness impulse arriving at the access input of memory block 3, whereby the binary code contained in the first line of memory block 3 arrives at its outputs. On a data readiness pulse, this binary code is written to register 9, from the outputs of which it is fed to the information inputs of the digital-to-analog converter 5, and from the digital-to-analog output. Converter 5 to the output bus 6 receives the discrete value of the analog signal proportional to the value of the input analog signal in the first 1 conversion. Thereafter, the discrete values of the analog signal, proportional to the values of the input analog signal, are formed in the subsequent conversion cycles. Invention Formula A device for recording analog output signals, containing an analog-to-digital converter connected by analogue to o five 0 five 0 five an analog signal input terminal connected by data outputs and data readiness output respectively to informational inputs and access of a memory unit connected by address inputs to counter outputs, a digital-to-analog converter connected by output to the output bus, input bus of the clock signal and in ( A new installation bus, characterized in that, in order to reduce the sampling error during the recording-reproduction process, a register is inserted in it connected by outputs to the information inputs of the digital-analog A converter connected by a reset input and a recording input, respectively, to the input bus of the installation and to the readiness output of data from the analog-1 digital converter and connected by information inputs to the outputs of the memory unit equipped with the mode input bus connected to its mode select input, and the frequency divider connected by the counting input to the input rp is not a clock signal and connected to the output from the counting input of the counter and the input quenching and converting analog-to-digital converter, equipped with connected its input reference voltage input pmnoy reference voltage coupled to the input reference voltage tsifroanalpgovogo transducer, wherein the input ptna installation connected to the reset inputs of the counter and a frequency divider.