SU231224A1 - STORAGE DEVICE ON CYLINDRICAL MAGNETIC FILMS - Google Patents

Description

Memory devices on cylindrical thin magnetic films are known that contain a memory block, a clock line, a number register, an address register, minimum and maximum levels of control currents, a local control device with a clock counter and coincidence circuits for starting minimum and maximum current levels management

The proposed device is characterized in that a trigger, a valve and a switch of single and zero inputs of a numerical register are introduced into it. A single trigger input is connected to the output of a clock counter, a single output to the inputs of a coincidence circuit that overloads the drivers of the minimum current levels, and a valve input, another input of which is connected to the clock pulse highway, and the output is connected to a zero input, respectively. trigger, with the counting input of the address register and with one of the switch inputs. The output of the clock counter is connected to the second input of the switch, and the zero output of the trigger is connected to the inputs of the coincidence circuits that start the drivers of the maximum current levels. This allows for automatic control of the storage device in the most severe mode of operation of the storage cells.

FIG. 1 shows the block diagram of the proposed storage device; in fig. 2 - time diagram of the operation of this device.

The storage device contains a memory unit / on cylindrical thin magnetic films. Circuit 2 of the formation of address currents can generate current pulses whose amplitudes correspond to the maximum and minimum levels of a given or practically achievable range of variation of the amplitudes of address currents. Circuit 3 of forming discharge currents can generate current pulses, the amplitudes of which also correspond to two levels of a given range of their change.

In the drawing, reference numerals 2, 3 denote coincidence circuits that start the shapers of minimum current levels,

positions 2z, 2 are coincidence circuits that trigger the drivers of maximum current levels.

Circuit 3 is controlled by a 4-digit register. The code of the number comes when working as part of

The digital computer is either manually dialed from the memory control panel to the number register from the 5 number code lines.

Useful signals from memory cells of memory 1 are amplified by amplifiers 6

sa, which selects the desired address depending on the address code recorded in the S address register. The address code goes to the register and from the code buses. The address when working as part of a digital computer or is dialed manually from the control center. Register 8 can operate in counter mode and has a counting input 10. When register 8 is operated in counter mode, all the addresses of memory block 1 are sequentially accessed. The local control unit 11 generates a sequence of commands for the memory. The device 11 receives the clock pulses from the trunk 12 clock pulses and commands from 13 commands.

In order to automatically detect inoperative cells, device 11 must contain a comparison circuit of the code received from the reading amplifier 6 with a given code and a clock interrupt circuit if these codes do not match.

In order to control the performance of the storage cells in the heavy mode, the memory device contains a clock counter 14, whose signal at output 15 appears after a certain number of n-pulses have arrived at its input 16. This number of pulses determines the number of cycles of repeated information recording in The hard mode described earlier. The input 16 of the counter 14 is connected to the highway 12 via a clock interrupt circuit and a heavy mode on circuit 11 in the device 11.

To carry out a single recording of information of one character after multiple recording of information of another character, the memory device contains a trigger 17 and a switch 18 single and zero inputs of the trigger register of the number 4. The single input of the trigger 17 is connected to the output 15 of the counter 14. the pulse input of which is connected via a delay line 20 to the clock pulse 12. The output of the valve 19 is connected to the counting input 10 of the register 8, to the zero input of the trigger / 7 and to the single input switching Chatel 18, with the second input of which is connected to the output 15 of the counter 14.

The single and zero outputs of the trigger 17 are associated with the schemes for generating address and discharge control currents in such a way that when the trigger 17 is in the definition of "1", the pulses of the address and discharge currents have amplitudes corresponding to the minimum levels of the specified ranges of their change; and when trigger 17 is in the "O" position, the amplitudes of these currents are maximum within these ranges.

All zero and single inputs of the register triggers 4 are combined with each other (this integration can be carried out, for example, through the input valves, which are not shown in the drawing, as can be considered.

that they are part of register triggers 4). The community of the single inputs and the total zero inputs of the register 4 are connected to the outputs of the two-channel switch 18, which connects each bus to either its one input or the other, and both buses switch simultaneously.

The sequence of clock pulses 21 through the heavy duty circuit

The device 11 is fed to the input 16 of the counter 14. The device 11, with the arrival of each clock pulse, performs a read-write cycle. The reading is performed at the leading edge of the address current pulse, and

write if the trailing edge of this address current coincides with the discharge current of the corresponding polarity.

At the pulse input of the valve 19 enters through the delay line 20 sequence

pulses 22, the delay time should be less than the time between two clock pulses, but greater than or equal to the read-write cycle time. Let in the register 8 the code is written, according to

which is addressed to (K-1) address. During the first (p-1) cycles, information is repeatedly recorded in a cell at maximum amplitudes of control current pulses. After the entrance

16 of the counter 14 will receive n pulses, at its output 15 a pulse of the pulse train 23. This pulse will transfer the trigger 17 to the state "1", and it will switch to the bus connecting the single or zero inputs of the trigger of register 4 via the switch 18, setting them to all in one of the stable states - “O or” 1, depending on the hollow switch 18. Thus, in this cycle, the information typed in register 4 will be recorded once, i.e. “O or” 1 depending on The position of the switch 18. This one-time entry b children carried out at a minimum actuating currents, as trigger

/ 7 is in the state "1.

For the 5th pulse of the pulse sequence 22, the valve 19 will be open, and this pulse will go to the counting input 10 of the register 8. The code in the register 8 will change to "1,

as a result, the X-th address will be selected by the decoder 7. The same impulse will set the trigger 17 to the position whereupon the valve 19 is closed for the passage of subsequent pulses. In addition, the same pulse from the output of the valve 19 will go through the switch 18 to the mud, which unites the inputs of the trigger register 4, opposite to those to which the pulse of the sequence 23 from the output 15 of the counter

14. The sequence of pulses 24 is the sequence of pulses at the output of the valve 19. The sequence of states 25 of the trigger 17 is simultaneously the sequence of states of the triggers of the register of these triggers). Subsequent (n-1) cycles will produce multiple entries at the K address, n-cycle will record once, then go to (Kt-1} address, etc. After the register 8 has been enumerated all possible code combinations, the device returns to the (K - I) address, while the entire memory unit will store the once recorded information 10 of the same character 26 - there is a sequence of pulses of the address current at (/ C-1) address; 27 - I am the address and 28 is at the (K + I) address; 29 is a sequence of pulses of 15 discharge current n and checking the operability of cells by "1, 30 - when checking by" O. The transition from sequence 29 to sequence 30 and vice versa is performed by changing the position of the switch 18.20 If the first reading at each address of the new address traversal cycle is control, then the received memory mode will be the heaviest for storage cells on cylindrical 25 thin films, since this is the reading of once written information with minimal control currents, which takes place after multiple recording information of the opposite sign into the adjacent AOR memory cells, produced at maximum control currents. The useful signal corresponding to the once recorded information must be reliably distinguishable against the background of interference and amplified by the reading amplifier 35. Signals from reading amplifiers 6, received on the first call after a transition to a new address, should be sent to the comparison device, all of them should be either signals "1 or signals" O in 40 depending on the position of switch 18. In the event that there are no signals (less than the threshold) or there are signals carrying opposite information, a device interrupting the clock triggers, and the code in register 6 and the comparison circuit, having an indication on the console, give the coordinates of the inoperative cells. ,, ij noe state of the flip-flop 17 and the moat 50 trigge- register 4 before moving on a heavy work mode may be any one cycle is set after one traversal of all addresses. Before turning on the comparison and shutdown scheme, it is useful to bypass all 55 addresses in a heavy mode of operation several times. 5 If you observe the output signal from single-bit storage cells on the oscilloscope screen, when the storage device is operating in a large mode, the resulting picture will give the maximum spread of signals in this bit, which may be necessary to know when adjusting. When operating in the described mode, due to the fact that the current pulses are odor-polar in all discharges, the electronic control circuits of the storage device and the power supply circuits will operate under the most severe conditions. So, the indicated mode is heavy not only for storage cells on cylindrical thin magnetic films, but also for storage control circuits and for power supply circuits. Therefore, the storage device debugged in the operation mode described in the present application is distinguished by high reliability and operability. The subject matter of the invention is a storage device on cylindrical magnetic films containing a memory block, a clock line, a number register, an address register, drivers of minimum and maximum levels of control currents, a local control device with a clock counter and matching circuits for starting the drivers of minimum and maximum levels of currents control, characterized in that, in order to provide automatic control of the storage device in the most severe mode of operation, I memorize A trigger, a valve and a switch for the single and zero inputs of the numeric register are entered into it, the single input of the specified trigger is connected to the output of the clock counter, the single output to the inputs of the coincidence circuit that start the drivers of the minimum current levels, and to the input of A gate, the other input of which is connected to the clock flow, and the output is connected to the zero input of the specified trigger, respectively, to the counting input of the address register and to one of the inputs of the mentioned reklyuchatel, the second input of which is connected to the output of clock pulse counter, and the zero output of said flip-flop is connected to the inputs sonpadeni circuits carried constituent formers maximum levels start currents.

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