SU1762397A1 - Switch - Google Patents

Description

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(21) 4880878/21 (22) 07/10/90 (23) 03.21.90 (46) 09/15/92. Bul №34 (75) V.I.Turchenkov (56) USSR Author's Certificate No. 1471302, -kl. H 03 K 17/08, 1987. USSR author's certificate I 1471301. cl. H 03 K 17/60. 1987

(54) SWITCH (57) SUMMARY OF THE INVENTION: the device contains 6 transistors (1-6), 8 resistors (7-14), 2 input buses (15, 16), 2 output buses (17, 18), 1 common bus ( nineteen). 2 Il.

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The invention relates to a pulse technique and is intended to pass one of two input pulses to the output.

Known switch containing a transistor, the emitter of which is connected to the first input bus, the collector - with the first output bus, the base - with the first output of the first resistor, the second resistor, the first output of which is connected to the second output bus.

A disadvantage of the known technical solution is its small area of use due to the impossibility of passing to the output only that input pulse, the leading front of which came later.

The purpose of the invention is to expand the field of use,

This goal is achieved by the fact that in the switch containing the transistor, the emitter and collector of which are respectively connected to the input and output buses, the base is connected to the first output of the first resistor and the second resistor connected to the second output from the second output bus, Fifth, sixth, seventh and eighth resistors; second, third, fourth, fifth and sixth transistors; the emitter of the second transistor is connected to the second input bus and through the third resistor to the base of the third transistor and collector the fourth transistor connected through the fourth resistor to the first output bus connected through the fifth resistor to the base of the fifth transistor whose collector is connected to the second output of the second resistor, to the base of the sixth transistor and through the sixth resistor to the emitter of the first transistor whose base is through the seventh resistor is connected to the collector of the third transistor, the emitter of which is connected to the common bus and emitters of the fourth, fifth and sixth transistors, the collector of which through the eighth resistor is connected to the base second about the transistor whose collector is connected to the second output bus.

The invention is illustrated in FIG. 1, which shows transistors 1-6, resistors 7-14, input buses 15 and 16, output buses 17 and 18, and a common bus 19.

Transistors 1 and 2 of the same type of conductivity, and the remaining transistors - the second type of conductivity. Consideration of the switch operation will start from the time ti, when the leading edge of the input pulse UBXI (see Fig. 2) arrived on the bus 15.

With this pulse through the resistor 12, the transistor 6 is saturated, from which the transistor 2 is saturated with the base current flowing through the resistor 14 and

the emitter of the saturated transistor 6 and the front of the output pulse on the bus 18 are formed on the collector of transistor 2. Simultaneously

with this, through the resistor 13, the transistor 4 is saturated, through the collector of which the current of the resistor 9 flows, ensuring reliable locking of the transistor 3.

Despite the fact that at time

0 t3, the trailing edge of the input pulse 11out1 on bus 15 is formed, the output pulse Uvich on bus 18 continues to form until time 14 - the formation of the trailing edge of the Ovx pulse,

5 due to the fact that the transistor 6 will remain in a saturated state with the current of the resistor 8.

At time ts, the first front of the pulse UBx on bus 16, from

0 which through the resistor 9 saturates the transistor 3 and when forming the leading edge of the UBXI pulse on the bus 15 at the moment of time te on the bus 15, by analogy, the output pulse of the output on the bus is formed

5 17 with the duration of the output pulse equal to the duration of the input UBXI.

Thus, the proposed switch passes to the output only that of the two input pulses, the front

The front of which came later and at the moment of forming the earlier input pulse, while it does not require a special power source for its operation and its consumption in the absence of input pulses is zero.

Claims (1)

Claims of the invention A switch comprising a first transistor whose emitter and collector are connected to the first input and output buses respectively, the base to the first output of the first transistor, the second resistor whose first output is connected to the second input bus, and the second output bus from L and h and yuschi and with the aim that 5 uses the third, fourth, fifth and sixth resistors and the second, third, fourth, fifth and sixth transistors, the emitter of the first of which is connected to the second input bus, the collector - to the second output bus, through the third the resistor is with the base of the third transistor, through the fourth resistor is with the first output of the nth resistor, with the base of the fourth transistor, the collector of which is connected via the sixth resistor to the base of the second transistor, and with the collector of the fifth transistor hist connected to the collector of the first transistor whose emitter is connected to the second terminal of the fifth resistor. and with the first output of the eighth resistor, the second output of which is connected to the collector of the third transistor and to the base of the sixth transistor, the collector of which u: h G li I} J.I L I JС connected to the second output of the first resistor, the emitter to the emitters of the third, fourth and fifth transistors and to the common bus. ji I d 1 + t