SU1737745A1 - Frame synchronization device - Google Patents

Abstract

The invention relates to telecommunications and can be used for personnel synchronization of receivers in digital information transmission systems with temporary compression. The purpose of the invention is to improve noise immunity. The device contains a generator 1 local clock frequency, the register 2 shift, the first D-trigger W, inverter 4, the first counter 5 pulses, the first element And 6, RS-trigger 7, the first element OR 8, the second and third elements And 9, 10, the second element OR 11, the fourth element AND 12, the third element OR 13, the second counter 14 pulses, the fourth element OR 15, the second D-flip-flop 16, the fifth element AND 17, the selector 18 of the clock signal. The device allows to isolate the sync characteristics in the input digital stream and form on their basis frame sync pulses, which allow synchronous and common-mode operation of the time frame distributor with the frame of the transmitting station. Due to the reduction of the registration threshold of the sync selector 18 when switching from the Synchronism Search mode to the Synchronization Hold and Selection mode by gating the output pulses of the sync signal selector 18, the device noise immunity is significantly increased. 1 il. Yo

Description

The invention relates to telecommunications and can be used for frame synchronization of receivers in digital information transmission systems with temporary multiplexing.

The purpose of the invention is to improve noise immunity.

The drawing shows a block diagram of the device frame synchronization.

The frame synchronization device contains a local clock generator 1, a shift register 2, the first D-flip-flop Z,

inverter 4, first counter 5 pulses, first element AND 6, RS-flip-flop 7, first element OR 8, second and third elements AND 9, 10, second element OR 11, fourth element AND 12, third element OR 13, second counter 14 pulses, the fourth element OR 15, the second D-flip-flop 16, the fifth element And 17, the selector 18 of the clock signal.

The device frame synchronization works as follows.

At the initial moment of time, when frame synchronization is applied to the device

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The supply voltage elements 2, 3, 5, 7, 14, 16, 18 are set to arbitrary states.

The entire diversity of the states of the elements of the frame synchronization device ultimately reduces to two states of the first counter of 5 pulses (Record mode and Downscale mode).

Suppose, at the input S of the first counter of 5 pulses, a potential corresponding to the Decrease Count mode is established. The pulses of the generator 1 local clock frequency, getting through the inverter 4 to the input C of the first counter 5 pulses, will reduce its content. When the contents of the first counter 5 pulses reach the number K (K is the number of MTF periods stacked in the half-bar), a pulse is removed from the output of the first element 6 and translates the P5-trigger7 into state 1, which opens the fourth for the output pulses of the synchro 18 selector 18 element And 12, thereby forming the first half-gate. During the passage of the first half-gate, due to the input to the input DL 1, the shift register 2 is filled with units. At the time of the occurrence of the unit in the k-th discharge of register 2 shift by the second element And 9, the reference pulse is separated, RS-trigger 7 is transferred to the state O, the fourth element And 12 is forbidden, the first half-row is over.

The reference pulse, arriving at the input C of the second D-flip-flop 16, will transfer it to state 1 and thereby establish at the input D of the first D-flip-flop Z a potential corresponding to a logical one. With the arrival of the leading edge of the local clock pulse (MSC), the first D-flip-flop 3 is set to state 1, while returning the second D-flip-flop 16 to its initial state. From this moment on, the potential corresponding to the Recording mode will be applied to the input S of the first counter of 5 pulses. After a half period of the MFC, the signal taken from the output of the inverter 4 will overwrite the contents of the storage device (a number equal to the frame duration in the MFC periods) into the first counter of 5 pulses. With the arrival of the next MTF pulse at the input C, the first D-flip-flop 3 will return to the initial state and at the input S of the first counter 5 pulses there will be a potential corresponding to the Decrease Count mode.

The occurrence of a unit in the k-th dereg register of the shift 2 not only initiates the completion of the first half-strobe and overwrites the first counter of 5 pulses, but also forms the leading edge of the second

strobe, opening for passage of the output pulses of the selector 18 of the clock signal, the third element And 10. The second half gate will continue until the shift register 2 is completely cleared, i.e. until it appears zero in its kth discharge.

Further, the operation process of the frame synchronization device is repeated. In this case, the reference pulses through the fourth

0 OR element 15 is fed to the C input of the second counter 14 pulses operating in the Counting to Increase mode. Since in the initial period of operation of the frame synchronization device, the output pulses of the clock selector 18 are generally not aligned with the strobe and do not go to the R input of the second counter 14 pulses , the contents of the second counter 14 pulses will increase. When the contents of the second counter 14 pulses will be equal to

0 M-digit number n, corresponding to the allowable number of additional missed sync signals, then the output of the fifth element I 17 is equal to one. In this case, the clock signal selector 18 will go over

5 into the registration mode of the unaffected sync signs and opens the fourth element I 12 for passing its output pulses. Such a state of the frame synchronization device corresponds to the Search synchronism search mode.

The first output pulse of the clock selector 18 passing through the fourth element I 12 will overwrite the first counter of 5 pulses and reset the second counter of 5 pulses of 14 pulses. Changing the code combination at the output of the second counter 14 pulses will set the output of the fifth element And 17 O, which will close the fourth element And 12 and lower the registration threshold

0 selector 18 clock. The frame synchronization device will go into Hold mode.

If a false sync signal is captured, then after the n cycles of the frame synchronization device operation, the second counter of 14 pulses will switch it to the Search for synchronism mode and a new sync signal will occur.

Assume that the device has entered sync and sync signals that have passed through the sync signal selector 18 are highlighted by the first half-line. In this case, the output signal of the selector 18 clock signal through the fourth element And 12 and the third and

5, the fourth elements OR 13, 15 will transfer the second D-flip-flop 16 to the state 1 and thereby ensure the rewriting of the first counter of 5 pulses. The same signal of the selector 18 clock signal through the fourth element

Both 12 and the second and third elements OR 11,13 will set the RS-flip-flop 7 to the state O, which will lead to the establishment of a potential shift at the DL input of the potential corresponding to a logic zero. In this case, the shift register 2 will not be filled with units up to the k-th bit and the reference signal will not be allocated to the second element 9. Thus, at the output of the fourth element OR 15, the reference pulse is replaced by the output pulse of the selector 18 of the clock signal and due to the offset of the rewriting time of the first counter 5 pulses, the lag of the phase of the reference pulse relative to the clock phase is eliminated. If the sync signal is input to the device for frame synchronization with delay during the second half-gate action, then during the strobe time, the first counter of 5 pulses is overwritten twice: the first time by the reference pulse selected by the second element 9 and the second time by the output pulse the selector 18 of the sync signal passed through the third element AND 10. A second rewriting of the first counter of 5 pulses eliminates the phase advance of the reference pulse relative to the phase of the sync signal.

Regardless of the instants of occurrence and the duration of the output pulses of the selector 18 of the clock signal, due to the scheme for overwriting the MST pulses of overwriting the first counter 5 pulses (D-triggers 3, 16 and inverter 4), the distance between the pulses at the inputs C and S of the first counter of 5 pulses will be constant, which will ensure the constancy of the rewriting conditions of the first counter of 5 pulses,

As the frame sync pulses, the output pulses of the first D-flip-flop 3 (inverted pulses of the counter of pulses 5) are used. Consequently, at the output of the frame synchronization device, as a CSI, we will have pulses generated either by the output pulses of the selector 18 of the sync signal (when the response of the selector 18 of the sync signal occurs during the first half-clock) or by reference pulses (in the absence of responses of the selector 18 of the sync signal within the strobe) or double pulses consisting of successive reference pulses and output pulses of the selector 18 of the sync signal (when the response of the selector 18 of the sync signal occurs during the period of This is the second polustrob).

Regardless of the nature of the generating signals described above, the length of the XSI is constant and equal to the reference period of the MFC (the latter is achieved by connecting the first and second D-flip-flops 3, 16).

Claims (1)

The invention of the frame synchronization device comprising a clock selector, the first and second pulse counters, the shift register, the first, second and third elements AND, and the RS flip-flop, characterized in that, in order to improve the noise immunity, the first and second D-triggers are entered, the first , second, third and fourth elements OR, fourth and fifth elements AND, an inverter and a local clock frequency generator, the output of which is connected to the C-inputs of the shift register and the first D-flip-flop and through the inverter to the C input of the first pulse counter, the outputs of the first N bits of which are connected to the inputs of the first element I, the output of which is connected to the S input of the RS flip-flop and the output of the RS flip-flop connected to the input of the DL shift register and the first input of the first element OR, to the second input of which and the control input of the clock selector the output of the fifth element I is connected, to the inputs of which are connected the outputs of the second pulse counter, while the outputs of the first and K-bits of the shift register are connected respectively to the first and second inputs of the second element AND, the output of which is connected to the first input of the fourth element OR, to the second input of which, as well as to the R input of the second pulse counter and the first input of the second element OR connected to the output of the third element OR, the inputs of which are connected to the outputs of the third and fourth elements AND, and the output of the k-th bit of the shift register is connected to the first input of the third element AND and The second input of the OR element, the output of which is connected to the R input of the RS flip-flop, and the output of the first element OR is connected to the first input of the fourth element AND, to the second input of which and the second input of the third element AND is connected to the output of the sync signal selector, the output of the fourth element OR is connected to the C input of the second pulse counter and the C input of the second D-flip-flop, the D-input of which is the input of the logical unit of the device, and the direct output of the second D-flip-flop connected to the D-input of the first D-flip-flop, the direct output of which is connected to the R-input of the second D-flip-flop and is the device's frame sync pulse output; the inverse output of the first D-flip-flop is connected to the control S-input of the first a pulse counter, the D inputs of the first N by the outputs of the frame duration in periods of the measurements of which are the installation clock frequency of the device. 0 / n memory ..- Jjfa 7 / L one- sh ABOUT