RU2003234C1 - Device for evaluation of telegraph signal reception quality - Google Patents

Description

a measurement time counter, and the output is connected to a counting input of a second counter, the outputs of which are connected via a read-only memory to the second inputs of the first and second comparison circuits.

Such a structure of the telegraph signal reception quality estimation apparatus allows to significantly reduce the measurement time under unfavorable communication conditions by automatically changing the measurement time in accordance with the actual level of signal reception quality at a fixed confidence value of the estimate.

The combination of knots and connections introduced into the inventive device was not found in the known technical solutions during the study conducted on the sources of patent and other scientific and technical information.

In FIG. 1 is a structural diagram of a device for assessing the quality of reception of a telegraph signal; Fig. 2 is a basic timing diagram of voltages.

The device comprises a fronts selector 1, the input of which is the input of the device, and the output is connected to the information input of the D-trigger 2 and to the synchronous reset input of the first counter 3. D-trigger output

2 connected via AND 4 element with reset inputs of the reverse counter 5 and counter

6 of the measurement time, the counting input of which is connected to the output of the edge selector 1. High-order output of the first counter

3 is connected to the input of the installation of the direction of counting of the reversible counter 5, the outputs of which are connected to the first inputs of the first comparison circuit 7, the output of which is connected to the input of the element And 4. The outputs of the counter 6 of the measurement time are connected to the first inputs of the second comparison circuit 8, the output of which is connected to the counting input of the second counter 9. The outputs of the second counter 9 are connected to the inputs of the register

10, the outputs of which are the outputs of the device, and with the inputs of the read-only memory 11, the first and second outputs of which are connected to the second inputs of the first and second comparison circuits 7 and 8, respectively. The reset input of the second counter 9 and the synchronization input of the register 10 are connected to the output of the element And 4. In this case, the output of the reference generator 12 is connected to the synchronization inputs of the edge selector 1 and the D-trigger 2, as well as to the counting inputs of the first counter 2 and the reverse counter 4 ,

In the proposed device, the selector 1 fronts can be performed, for example, according to the known scheme. As a D-trigger

2, you can use the K555TM2 chip, the first counter 3, the K555IE18 chip, the reverse counter A, the K531IE17 chip, comparison circuits 7 and 8, the K555SP1 chip, read-only memory 11, the K155REZ chip. The counter b of the measurement time and the second counter 9 could be performed on the 564IE10 chip, the register 10 on the 564IR9 chip.

A device for evaluating the quality of reception of a telegraph signal operates as follows.

The binary signal from the output of the threshold device of the demodulator (Fig. 2a) is fed to the input of the edge selector 1, to the synchronization input of which the clock pulses are supplied from the output of the reference generator 12 (Fig. 26) with a period m times less than the nominal duration Г0 of the chip. In this case, each package is divided into m clock intervals, where m is selected equal to 8 ... 32 (in Fig. 2 m 8). After each edge of the input signal, a pulse (Fig.2c) of duration T0 / t is generated at the output of the edge selector 1, which is fed to the synchronous reset input of the first counter 3. The time intervals between the next two successive output pulses of the edge selector 1 depend on the signal reception quality : in the absence of interference, they are equal to k T0, where k is an integer, and in the presence of interference, the greater the deviation from this value, the smaller the signal-to-noise ratio. The deviation sign does not contain information about the quality of signal reception, it is characterized by the average module of these deviations, which, due to the periodically phase of the edges of the parcels, can take values in the range from One II.

The first counter 3 has a counting factor t. In the absence of parcel fronts, a logical zero is present at its synchronous reset input (Fig.2c), therefore, the first counter 3 does not reset, and the voltage generated at the output of its high-order bit when dividing the clock frequency Is a meander with period t0 (Fig. 2e). This voltage is supplied to the bypass of the installation of the counting direction of the reverse counter 5, which is clocked by the output pulses of the reference generator 12. If there is a logic zero at the output of the highest order of the first counter 3, the reverse counter 5 operates in the addition mode, and in the presence of a logical unit, in the subtraction mode (on the

Fig. 2e shows the decoded states of the bits of the reverse counter 5). Since, in the absence of sending edges, the durations of the addition and subtraction intervals in the reverse counter 5 are the same (Figs. 2e, e), at the moment the reverse counter 5 changes from the subtraction mode to the addition mode the same number appears in it.

After the occurrence of the next sending edge (phi | .2a), a pulse is generated at the output of the edge selector 1 (Fig.2c), as a result of which the first counter 3 (fs.2d) is synchronously reset by the positive edge of the next clock pulse. In this case, the signal at the high-order output of the first counter 3 turns out to be phased with the last edge of the transmission. If the next edge appears after the time interval m0 (to within one clock interval), the voltage from the output of the high order of the first counter 3 retains the shape of the meander, the phase of which is not changed (figa, c, e, Fronts 1, 2), and the durations of the addition and subtraction intervals of clock pulses in the reverse counter 5 remain the same. Therefore, the number recorded in the reverse frequency 5 does not change at the moment of transition from the subtraction mode to the addition mode

With a decrease in the time interval between two subsequent sub-fronts by D clock intervals (A is an integer, 0 A m / 2), the next sending edge, appearing in the interval from k r0 - T0 / 2 to k r0, causes a premature reset of the first counter 3 (fsh.2a, v, d. fronts 3, 5), the duration of the unit section of the output voltage of the first counter 3 preceding this edge decreases by A clock cycles, and the duration of the subtraction interval in the reverse counter 5 is also reduced. recorded in reverse counter 5 in mom nt change from the adder subtractor in mode A is added (2e).

As the time interval between the next two successive fronts increases by A of the clock intervals, the next front comes in the interval from kr0 to k r0 + To / 2 (fig. A, c, e front 4). As a result of the reset of the first counter 3, the duration of the zero voltage section at the output of its highest order increases on A of the clock intervals (Fig. 2d front 4), causing a corresponding increase in the duration of the addition interval in the reverse counter 5. To the number recorded in the reverse counter 5 at the time transition from the subtraction mode to the addition mode, A is added

Thus, the number recorded in the reversible counter 5 at the moment of its transition from the subtraction mode to the addition mode, upon arrival of each edge, increases by the magnitude of the module of the phase deviation of this front from the phase of the previous front. As a result, the sum of the edge deflection modules is accumulated in the reversible counter 5. In parallel, in the counter 6 of the measurement time, the number of edges of the parcels received in the current measurement cycle is counted.

The numbers recorded in the reversible counter 5 and the counter b of the measurement time are analyzed using comparison schemes 7 and 8, and the analysis determines which of the possible gradations of the error coefficient when receiving a binary symbol corresponds to the actual signal reception quality. Possible gradations of the error coefficient are sorted through the measurement cycle sequentially, starting from zero gradation, which corresponds to the worst signal reception quality. The number of the current gradation i is stored in the second counter 9, from the output of which it goes to the address input of the read-only memory 11. At this address about the read-only memory 11 two numbers Mi and NI are stored, which are supplied respectively from the first and second outputs of the read-only memory memory 11 to the second inputs of the first and second comparison circuits 7 and 8 The number NI is chosen equal to the minimum number of edges of the bursts necessary for the correct assessment of the 1st gradation of the error coefficient with a selected confidence level of By chance. With such a number of edges and a reception quality corresponding to the 1st gradation of the error coefficient, the sum of the modules of the deviations of the phase of the edges with confidence takes values within a certain confidence interval. The number Mi is chosen equal to the lower boundary of the given confidence interval.

At the beginning of the measurement cycle, the reversing counter 5, the measuring time counter 6 and the second counter 9 are in the zero state, while the number Mo is supplied from the outputs of the read-only memory 11 but the second inputs of the first comparison circuit 7. and the second comparison circuit 8 is N0. Both numbers correspond to the zero gradation of the error coefficient (the largest possible error coefficient). The signals at the outputs of the comparison circuits 7 and 8 have a unit level if the numbers on their first

inputs there are more numbers on the second inputs, and zero level otherwise. Therefore, at the beginning of the measurement cycle, logic zeros are present at the outputs of the comparison circuits 7 and 8. With the arrival of the sending fronts in the device, the counting of their number and the sum of the deviation moduli begins.

If the actual reception quality corresponds to zero gradation, then the sum of the edge deviation modules coming from the outputs of the reverse counter 5 to the first inputs of the first comparison circuit 7 at the moment the reverse counter 5 changes from the subtraction mode to the addition mode will exceed Mo earlier than the number of sending edges - the measurement time arriving from the outputs of the counter 6 to the first inputs of the second comparison circuit 8 will exceed N0. After exceeding the sum of Mo and the arrival of the next edge, the output pulse of the edge selector 1, delayed in the D-flip-flop 2 for one clock interval, will go to the second input of the And 4 element at the moment when the first input of the 1/4 element from the output of the first comparison circuit 7 a logical unit is supplied. The delay in the D-flip-flop 2 is necessary to compensate for the delay of the signal in the first counter 3 and the reverse counter 5. At the output of the element And 4 a pulse is generated (Fig. 2d), by which the number of the gradation of reception quality is transferred from the second counter 9 to register 10, and the reversing counter 5, the measuring time counter 6 and the second counter 9 are reset (Fig. 2e, e). The current measurement cycle ends and a new cycle begins.

If the actual reception quality is above zero gradation, then the number of received fronts will exceed M0 before the sum of the deviation moduli reaches M0. When N0 is exceeded, the output of the second comparison circuit 8 exhibits a positive voltage drop, over which the number recorded in the second counter 9 increases by 1. At the outputs of the constant memory, as a result

address changes appear, the numbers Mi and NI corresponding to the first gradation of the error rate. Since, with the improvement of the reception span, a longer measurement time is required to evaluate it with a fixed confidence level, NI N0. Therefore, after increasing the gradation number by 1, the output of the second comparison circuit 8 is again set to logic zero.

The described operations of accumulating the sum of the deviation modules, counting the number of received fronts and increasing by 1 current moment of the quality gradation (increasing the gradation number corresponds to an increase in reception quality) continue until the sum of the deviation modules exceeds MJ earlier for any i-th gradation, than the number of fronts - NI (Nj is always greater than Mi). Exceeding the sum of the modules by the MI number means that 1-gradation most correctly evaluates the actual reception quality. Therefore, after exceeding, as described above for zero gradation, the number i is transferred from the second counter 9 to the register 10, in which it stores the entire next measurement cycle, and the current cycle ends. The number of fronts received during a given measurement cycle ranges from Ni-1 to Mi; it determines the actual duration of the cycle.

Thus, in the proposed device, the measurement time automatically changes in accordance with the actual level of reception quality and does not exceed the interval during which the minimum number of edges of the packets is received, which is necessary for a correct assessment of the actual reception quality with a fixed confidence level. Due to this, the measurement time is reduced by 5 ... 6 times when evaluating the quality of reception of the telegraph signal under adverse communication conditions.

(56) Copyright certificate of the SSSR No. 1573549. cl. H 04 L 12/26. 1989.

Claims (1)

The claims TELEGRAPHIC SIGNAL RECEIVING QUALITY DEVICE, comprising a edge selector, the output of which is connected to the information input of the D-trigger, the synchronous reset input of the first counter and the counting input of the measurement time counter, a reversible counter, the input of which the counting direction setting is connected to the high-order output of the first counter and the counting input is combined with the counting input of the first counter, the synchronization inputs of the edge selector and the D-trigger and is connected to the output of the reference generator, connected in series there is a second counter and register, characterized in that the first and second comparison elements, a read-only memory unit and the AND element are inserted into it, the first inputs of the first comparison element are connected to the outputs of the reversible counter, and the output is connected to the first input of the second element I. the second input which is connected to the output by the D-outputs of the measurement time counter, and trigger, and the output is connected to the inputs of the reset output, the counting input of the second reversible counter, the measurement time counter and the second counter and to the input register synchronization, first pass5 with the first inputs of the first and the second comparison element connected to the comparison elements counter, the outputs of which are connected via a permanent storage unit to 8x. Go the output is connected, the counting input of the second the first inputs of the first and counter, the outputs of which are connected via a permanent storage unit to Fig / to Gl