SU1737710A1 - Frequency multiplier - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation, computing and measurement technology. The purpose of the invention is to increase the multiplication factor by comparing the duration of the input signal period with the control values, dividing the whole part of the result of the first division by 2m, where m 0, 1, 2 ... is the number of exceeding the control values, and in the next period of the input read signal part of the result of the second division pulses of the reference frequency. The frequency multiplier contains the frequency generator 1, the counters 2 and 5, the frequency divider 3, the input bus 4, the storage register 6, the output bus 7, the shift block 8, the priority block 9, the pulse shaper 10. 1 il.

Description

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about

The invention relates to a pulse technique and can be used in automation, computing and measurement technology.

The purpose of the invention is to increase the multiplication factor by comparing the duration of the input signal period with the control values, dividing the whole part of the result of the first division by 2m, where m 0, 1, 2 ... is the number of control values exceeded, and B the next period the input signal for reading the integer part of the result of the second division of the reference frequency pulses.

The drawing shows a block diagram of the device.

The device contains the reference frequency generator 1, the first counter 2, the frequency divider 3, the input bus 4, the second counter 5, the storage register 6, the output bus 7, the shift block 8, the priority block 9, the pulse shaper 10.

The output of the reference frequency generator 1 is connected to the synchronization input of the first counter 2 v by the input of the frequency divider 3, the installation input in O 1 of which is connected to the input of the yciai-tongue of the second counter 5, the device input bus 4 and the storage register 6. The information inputs of the latter are connected to the information outputs of the second counter 5, and the information outputs to the information inputs of the shift unit 8, the outputs of which are connected to the information inputs of the first counter 2, and the most significant bits of the storage register 6 are connected to the inputs of the priority block 9, the outputs of which are connected to the control inputs of the shift unit 8.

The output of the first counter 2 is connected to the input of the pulse former 10, the output of which is connected to the preset input of the first counter 2 and the output bus 1 of the device.

The device works as follows.

The frequency of the input signal within tnch. fx 5 tvch., where Tn.h, fe.4 - frequencies of the lower and upper limits of the working range of the frequency multiplier. During the period TXJ of the input signal from the bus 4 using the counter 5 count the number of pulses of the reference frequency f0 of the generator 1 of the reference frequency, divided by. The counter 5 for each pulse from the bus 4 is set to the state O, .. O, At the end of the period Txi in the counter 5 the number NXJ fo TXi / K0 is formed.

The number NX defines the integer part of the result of the division of the Hz | as the code contained in the counter 5. The value of

the initial multiplication factor K0 is determined by the division factor of the frequency divider 3 used in the frequency division mode of the reference frequency generator 1; the leading edge of the pulse of the end of the period Txi memorizes the integer part of the result of NLJI division in register 6. The working range of the durations of the periods Txi are several subranges, the beginning of each of which coincides with the pulse of the input signal. At the end of the TXI period, a subband is defined in which the Txi period ends. These are both ... as they compare the duration of the TX period | with several control values, Tv.ch.

With

 f x f in

change

MC | can be performed in the s lower bits of register b, and in the high-order s-th bit there must always be a log. 1. When Tv.ch. with fe.4

+ 1

fx

Where

Oh, 1, 2 ... n, and the higher bits of register 6 are numbered s + J, log. 1 of the corresponding highest bit s + j determines the subband to which the length of the measured period Txi belongs. The priority block connected to the n-high register bits, as well as its s-th bit, performs the function of comparing the duration of the period TXi with several reference values. In this case, the most significant bit of register 6 has the highest priority. Thus, the signal log. 1 is present on one of the (n-f-1) -th output of priority block 9. This signal shifts the N4i code towards the lower bits to ji bits, where ji is the number of the register register 6 s log. 1 highest priority. This ensures the division of the integer part of the result of the first division by the number j 2m in accordance with Txi belonging to one or another sub-band, where m ji is the number of exceedances of the established reference values,

In the next period, Tx, + 1 of the input frequency reads the integer part of the result of the second division by clock pulses. This is done as follows. Counter 2 is organized, for example, to subtract. At some point in time at its loan exit, a signal is generated, indicating that all its bits are set to 0 ... 0. This signal triggers the imaging unit 10, designed to increase the reliability of writing the code from the output of the shift block 8 into the counter 2. Next, this code is read to the value

0 ... 0 and so on. The output signal of the driver 10 is also fed to the output bus 7. Depending on ji, the multiplication factor is determined by the expression: K. The conversion error of the device according to this method is within

Ov.ch. dx -2- .h.

Claims (1)

The invention A frequency multiplier comprising a frequency generator, the output of which is connected to the synchronization input of the first pulse counter and the input of the frequency divider, the installation input of which is connected to the input bus of the device and the installation input of the second pulse counter of which the synchronization input is connected to the output of the divider frequencies, and information outputs - with information inputs of the storage register, the recording input of which is connected to the input bus of the device, the presetting input of the first counter pulses connected to the output bus device, characterized in that, in order to provide the possibility of increasing the multiplication factor, a shift block, a priority block and a pulse shaper are inputted into it, whose input is connected to the output of the first pulse counter, and the output is connected to the output bus of the device, the information outputs of the storage register are connected to the information inputs of the shift unit, the outputs of which are connected to the information inputs of the first pulse counter, n the most significant bits n g -s, ten qaHoa l. one ; T.ch. To 15 loga TB.X. s IOQ2 incl. To where tnch and tvch are the frequencies of the lower and upper limits of the working range of the frequency multiplier; fo is the number of reference frequency pulses; Co is the initial multiplication factor, the storage register is connected to the inputs of the priority block, the outputs of which are connected to the control inputs of the shift block.