SU1720154A1 - Majority member - Google Patents

Abstract

The invention relates to automation and computing and can be used in the construction of control systems. The purpose of the invention is to simplify the majority element. The element contains an inverter 2, a logic element 5, inputs 10-12, output 13. Introduction to the composition of the majority element of the inverter, made on CMOS transistors 3 and 4, and the resistance of open transistors 3 and 4 in. 2 (K-1) times the resistance of the open transistor of the logic element 5, where K is the ratio of the supply voltage to the threshold voltage, and allows for different values of signals at the 10th and 11th inputs of the majority element to set its output 13 by the value at the input 12. 1 Il.

Description

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The invention relates to automation and computing and can be used in the construction of control systems.

A majoritarian element is known that contains an AND-OR-NOT element, the first input of the majority element being connected to the first inputs of the first and second groups AND AND-OR-NOT elements, the second input to the second inputs of the second and third groups AND AND-OR elements , the third input is with the second and first inputs of the first and third groups AND AND-OR-NOT respectively, and the output of the majority element is connected to the output of the AND-OR-NOT element.

A disadvantage of the known majority element is the redundancy of the equipment, since its implementation on CMOS transistors requires 10 transistors.

Closest to the present invention is a majority element consisting of a first logic element made on two n-type MOS transistors and two p-type MOS transistors, and a second logic element made on three n-type MOS transistors -type, in each logic element the drain and source of the first p-type MOS transistor are connected to the power bus and the source of the second p-type MOS transistor, the source and drain of the first n-type MOS transistor are connected respectively to the common bus and the source of the second M P n-type transistor, the drain of which is connected to the source of the first p-type transistor, in the second logic element the drain and source of the third p-type MOS transistor are connected to the source of the first p-type transistor and the drain of the third n-type transistor, the source of which is connected to the drain of the first n-type transistor of the same element, the first input of the majority element is connected to the gates of the first transistors p- and p-types of both logic elements, the second input - to the gates of the second transistors p- and p-type of the first logic element and the gates x transistors p- and p-type of the second, the third input - with the gates of the second transistors p- and p-types of the second logic element, the output of the majority element connected to the drains of the first n-type transistors of both logic elements, as well as the drain of the third transistor n-type second logical element.

The disadvantage of this majority element is the redundancy of the equipment, since its implementation requires 10 MOS transistors.

The purpose of the invention is to simplify the majority element.

This goal is achieved by the fact that in a majority element consisting of an inverter and a logic element made on two n-type MOS transistors and two p-type MOS transistors, in a logical element the source and drain of the second p-type transistor are connected respectively to

the power bus and the source of the first p-type transistor, the source and drain of the second n-type transistor are connected respectively to a common bus and the source of the first n-type transistor, the drain of which is connected to the drain

the first transistor of p-type and the output of the logic element, the first input of the majority element is connected to the gates of the first transistors n- and p-types of the logic element, the second input - to the gates of the second transistors n- and p-types of the logic element, and the third input - to the input the inverter, the output of the majority element is connected to the output of the inverter and logic element, and the resistance of the inverter’s open transistor exceeds

the resistance of the open transistor of the logic element is more than 2 (k-1) times, where k is the ratio of the supply voltage to the threshold voltage.

The introduction of the inverter to the majority element, made on MOS transistors with increased resistance, allows for different values of the first and second inputs of the majority element to set its output by value

at the third entrance, resulting in a simplified element.

The drawing shows the scheme of the proposed major element.

The majority element 1 contains an inverter 2, made on a p-type MOSFET and n-type 4 transistor, and a logic element 5, made on p-type MOS transistors 6 and 7 and n-type 8 and 9. The drain and source of the transistor b p-type are connected respectively to

the p-type power line and the drain of the p-type transistor 7, the source and the drain of the n-type transistor 9 are respectively connected to a common bus and the source of the n-type transistor 8, the drain of which is connected to the source of the p-type transistor 7 and

the output of the logic element 5. The input 10 of the majority element 1 is connected to the gates of transistors 7 and 8, the input 11 to the gates of transistors 6 and 9, the input 12 to the input of the inverter 2, the output of which is connected to the output of the logic element 5 and the output 13 of the majority element 1 .

The majority element works as follows.

If the inputs 10 and 11 are logical values 00 (11), then transistors 6 and 7 are open (closed), and transistors 8 and 9 are closed (open). Then, at the chosen ratio between the resistance R of the open transistor of the inverter 2 and the resistance r of the open transistor of the logic element

5 (R 2 (k-1) r, where k Vn / VT, Vn is the supply voltage; VT is the threshold voltage) at output 19 will be the value of a logical unit (zero) regardless of the value at the input 12. The value at inputs 10 and 11 are opposite, then one of the transistors is closed

6 and 7 and one of the transistors 8 and 9 is closed, thus the value at output 13 is determined by the value at input 12 and will be equal to one, if input 12 is a logical zero, and zero, if input 12 is one.

For example, when the supply voltage is 5V and the threshold 1B, the ratio of the resistances of transistors 8 and 9 and 3 or b, 7 and 4 will be 1: 8 respectively. If the inputs 10 and 11 have the values 1 (transistors 8 and 9 are open) and the input 12 is O (the transistor 3 is open), a voltage divider of two transistors 8 and 9 and transistor 3 is formed, with the result The ratio of resistances of these transistors, the voltage at output 13 will be 1V, i.e. voltage of logical zero. In the opposite case (at inputs 10 and 11, signals O, and at input 12 - 1) the voltage will correspond to 4V, i.e. voltage of logical unit. Note that by increasing the ratio of the resistances of these transistors (for example, 1:10), we will further approximate the voltage at output 13 to the ideal values of logical zero and one, respectively. Notice

except that when the inputs 10 and .11. the values of the signals are different, the value at output 13 is determined by the output value of inverter 2, i.e. opposite to the value at input 12 and at the same time equal to the ideal value of logical zero or one, respectively. .

The implementation of the proposed major element requires 6 MOS transistors versus 10 MOS transistors in the prototype. those. 40% simplified equipment.

Claims (1)

The formula for acquiring the Majority element, consisting of an inverter and a logic element, RI filled on two pairs of CMOS transistors of n- and p-types, in a logical element the sources of the second transistors p- and n-types are connected respectively to the power bus and common bus, their drains - with the origins of the first transistors of p- and n-types, the drains of which are connected to the outputs of the logic element, the output of the inverter and the output of the majority element, the first input of which is connected to the gates of the first transistors of the p- and n-types of logic element, the second entrance - with for p-and n-type logic element creations of the second transistor, and the third input with the inverter input, characterized in that, for the purpose of simplification, the resistance of the open transistor p- and p-type inverter is 2 (k-1) times The resistance of an open transistor is a p- and n-type logic element, where k is the ratio of the supply voltage to the threshold voltage, and the sources of the p- and p-type transistors of the inverter are connected to the power bus and the common bus respectively.