SU1097162A1 - M-digit inverter - Google Patents

Abstract

the t-VALUE INVERTER contains two resistors and two CMOS transistors, the gates of which are connected to the input of the source inverter and the substrate to the corresponding power lines, and the drains are respectively connected at the p-type CMOS transistor to the first output of the first resistor and CMOS- transistors with an n-type channel to the first one of the second resistor, characterized in that, in order to extend the functionality, two are introduced into it. additional CMOS transistors, the gates of which are connected to the input of the inverter, and the third resistor, the first output of which is connected to the second end of the first resistor, to the source S and the substrate of the additional CMOStransistor with the p-type channel, and the second output to the second end of the second resistor, the source and the substrate of an additional CMOS transistor with an n-type channel, the drains of additional CMOS transistors are connected to the output of the inverter. O) with

Description

The invention relates to the field of computer technology and microelectronics and can be used to build multi-valued devices on MOS transistors.

Multivalued CMOS transistors are known, containing basic decoders, two-digit inverters and a coder of corresponding significance, for example, a three-digit inverter consisting of two basic decoders, two two-digit inverters and a three-digit coder.

A disadvantage of the known devices is their complexity.

A three-digit inverter is also known. It contains two resistors and two. CMOS transistors, - the gates are connected to the input of the device, the sources and the substrates are connected to the corresponding power lines, and the drains are connected to the first output of the first M-transistor. the resistor and the MOSFET with an n-type channel to the first terminal of the second resistor, and the second terminals of the resistors are connected to the output of the device.

The underside of this inverter are narrow functional networks, due to its low value, which limits the effect of its use.

The purpose of the invention is to expand the functionality of the device.

This goal is achieved by the fact that a T-digit inverter on a CMOS transistor contains two resistors and two CMOS transistors, the gates of which are connected to the input of the device, the sources and the substrate are connected to the corresponding power lines, and the drains are connected respectively to the CMOS transistor a p-type channel to the first output of the first resistor and a n-type CMOS transistor to the first output of the second resistor, introduced two additional CMOS transistors, the gates of which are connected to the input of the device, and a third resistor whose first output By connecting the second vshodu first resistor, to the source and substrate KMOPtranzistora additional p-channel type, and a second terminal connected to the second terminal of the second resistor, the source and substrate KMOPtranzistora additional channel of n-type ,. Additional CMOS transistors are connected to the output of the device.

The drawing shows a schematic diagram of the proposed t-valued inverter in CMOS transistors.

the t-significant inverter on CMOS transistors contains two resistors 1.2 and two CMOS transistors 3, 4, the gates of which are connected to the input 5 of the device, sources and substrates to the corresponding buses 6, 7 of the power supply, and the drains are respectively connected at CMOS- a p-type transistor 3 to the first output of the first resistor 1 and a CMOStransistor 4 with an n-type channel to the first output of the second resistor 2, two additional CMOS transistors 8,9j whose gates are connected to the device 5, and the third resistor 10, the first pin of which is connected to the second pin of the first the first resistor 1, the source and the substrate of the additional CMOS transistor 8 with the p-type channel, and the second output to the second output of the second resistor 2, the source and the substrate of the additional CMOS transistor 9 with the n-type channel, the drains of the additional CMOS transistors 8, 9 are connected to the device output 11, CMOS transistors 3, 4 are connected to the first and second additional outputs 12, 13, respectively, and the sources of the additional CMOS transistors 8.9 to the third and fourth additional outputs 14, 15, and fifth additional, respectively. exit 16 may be b obtained by combining the first and second auxiliary outputs 12, 13.

The t-digit inverter on CMOS transistors operates as follows. The input 5 of the device receives signals in the form of a DC voltage in the range from 0 volts to the voltage of the power source E, which in logical terms corresponds to the alphabet E (0,1,2,3). Suppose that the input signal of a four-digit inverter on a CMOS transistor is O, i.e. the voltage Uj at the input 5 is within the limits O U u U U then where and J, is the voltage of the threshold of the CMOS transistors, in this case the CMOS transistors. with n-type channels 4 and 9 are closed, because the voltage on their gates does not exceed U then a CMOS transistor with p-type channels 3 and 8 due to the fact that the voltage on the thieves relative to the potentials of their sources is less than schuyu and others, are open. As a result, at the additional outputs 12, 13, 14, 15 and the main output 11 of the inverter, the voltage is close to Ep, which corresponds to the logical signal 3). If the input signal is fl), i.e. the voltage Ug at the input 5 of the device is within the range of CMOS transistors with the p-type channel 3 and 8 due to the fact that the voltage at the gates of these CMOS transistors with respect to the potentials of their sources is still smaller by the amount exceeding and The others are open, the p-type 4-channel CMOS transistor is due to the fact that the voltage on its gate is higher and then open, and the additional CMOS transistor with the n-type channel is closed, because the voltage on its gate is relative to to the source potential of this CMOS transistor is less than U As a result, Riva case between the supply rails 7 and 6 is turned on a voltage divider of resistors razovanny 1, 2 and 10, which ratings are equal, that provides a connection point of the resistor voltage equal to E, respectively, 1/3, 2/3 and TU. By virtue of the above, the voltage at the first additional output 12 of the four-digit inverter is still close to E, which corresponds to the alpha value 3, at the second additional output 13 is {0, because the n-type 4-channel CMOS transistor is in a conducting state at the third additional output 14 - 2/3 E (logical value 2), at the output of a quarter of an additional 15-1 / 3 „or 1 in a four-digit alphabet, and at output 11 due to the fact that the additional CMOS transistor with a p-channel Type 8 open and auxiliary CMOS transistor the a-type scarlet 9 is closed — also 2/3 E (logical value 2J). Now let the signal at input 5 be 2), i.e. the voltage at the input 5 of the four-digit inversion of the torus is within 1/3 E and 2/3 E. + Ular For this state, the voltage at the first additional output 12 of the device, as in the previous case, is close to E „, I.e. equal to the logical value {3}, at the second additional output 13 is still 0, at the third and fourth additional outputs 14 and 15, respectively 2/3 Е „(logical value 2) and 1/3 Ер (logical value {1) on output 11 due to the fact that the additional CMOS transistor with a p-type channel 8 is closed, and the additional CMOS transistor with an n-type channel 9 is open, the voltage is 1/3 E (logical value ilj). Finally, let us consider the operation of a four-digit inverter on CMOS transistors with an input signal equal to 31, i.e. when the voltage U at input 3 is within 2/3 E, + + Uj, jj and vk Ef ,. In this case, the output voltages are equal to O on all outputs 11, 12, 13, 14, and 15 of the device, since all CMOS transistors are closed. When combining the first and second additional outputs 12 and 13, a fifth additional output 16 is formed. In this case, the four-digit inverter is converted to binary and the characteristic input of the 5th-fifth additional output 16 is completely identical with the characteristic of a standard CMOS inverter. Thus, at low hardware costs (two pairs of complementary CMOS transistors), the proposed four-digit inverter allows you to invert the input signal in the quaternary alphabet. In addition to this, it can be used to implement the full set of one-time four-digit threshold functions and two four-digit functions of one variable. The technical and economic effect in the proposed device consists in expanding its functionality, which makes it possible to reduce the range of devices used.

one

h.

-i

ig

-0; v

75

n) t

/ /

Claims (1)

Makoto Hatta, Itsuo Takanami and Katsushi Inoue. A realization of ternary logic functions by using cellular arrays. Proceedings of 10-th International Symposium on Multiple Valued Logic, Evanston, 1980, p. 45- ^ 64. / (54) (57) m-VALUE INVERTER, containing two resistors and two CMOS transistors, the gates of which are connected to the inverter input ^ sources and substrates to the corresponding power buses, and the drains are respectively connected to the CMOS transistor with a p-type channel to the first output of the first resistor and a CMOS transistor with a p-type channel to the first output of the second resistor, characterized in that, in order to expand the functionality, two additional CMOS transistors are introduced into it, the gates of which are connected to the inverter input, and the third resistor , first the output of which is connected to the second terminal of the first resistor, to the source and substrate of an additional CMOS transistor with a ρ-type channel, and the second terminal to the second terminal of the second resistor, source and substrate of an additional CMOS transistor with an η-type channel, the drains of additional CMOS transistors are connected to the inverter output.