SU1492467A1 - Tristable element using cmi transistors - Google Patents

Abstract

The invention relates to the field of computing and can be used in digital integrated circuits as an output device. The aim of the invention is to simplify the device by reducing the number of external leads and the corresponding control actions. For this purpose, a third 6N-type MOS transistor is introduced into the device, and the NAND-1 element is provided with an additional output 14. The device also contains two 2.3 p-type transistors and the first 4 and second 5 N-type transistors. By using the additional output 14 of the NANDLE 1 element and the third N-type transistor 6, which shunt the gates of the output transistors 2 and 4, the element operates with three states with a smaller number of external leads. 1 il.

Description

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The invention relates to computing and can be used in digital integrated circuits as an output device.

The aim of the invention is to simplify the device by reducing the number of external leads and the corresponding control actions.

This goal is achieved by introducing an additional transistor and using the additional output of the NAND element, whereby the element with three states requires a smaller number of transistors to realize.

The drawing is a circuit diagram of an element with three states on a CMOS transistor.

The device contains the element AND NOT 1 two transistors 2-3 p-type and three transistors 4-6 p-type. The input terminals 7-8 of the device are the inputs of the NAND element 1, the output 9 of which is connected to the gate of the first p-type transistor 2 and the drain of the third p-type transistor 6. The sources of all the p-type transistors are connected to the power supply bus 10. The sources of the first 4 and second 5 n-type transistors are connected to the common bus 11. The first transistors 2 and 4 of both types are connected in series and their common point is connected to the output terminal 12 of the device.

The gates of the second transistor 3 p-type and the third transistor 6 p-type are connected to the second input terminal 8 of the device. The second 5 and third 6 n-type transistors are connected in series, and their common point 13 is connected to the gate of the first n-type transistor 4.

The NAND element 1 is provided with an additional output 14, which is a common point of series-connected transistors 15 and 16 of the n-type of this element. The AND-NE element is also connected between the power supply bus 10 and the common bus 11. The drain of the second transistor 3 is p-type and the gate of the second transistor 5 of the p-type are connected and connected to the auxiliary output 14 of the AND-HE element 1.

The device operates as follows.

The input terminals 7 and 8 are respectively supplied with information and control signals. When the input terminal 8 signal logical0

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I-NOT 1 copies are set to high voltage levels, regardless of the value of the information signal.

At the same time, the first p-type transistor 2 is closed by a high voltage level from output 9 of the NE-I element 1, and the first p-type transistor 4 is closed by a low voltage level from the common point 13 of the transistors 5 and 6 of the p-type, since the second transistor The 5 p-type is opened by a high level signal from the additional output 14 of the element AND-NOT 1. In this state, the output terminal 12 of the device is disconnected from the power bus 10 and the common bus 11 and is in a state with a high output impedance - the third state.

When the control signal supplied to the second input terminal 8 of the device corresponds to logical 1, a low level signal is established at the auxiliary output 14 of the AND-1 element 1, the second transistors 3 and 5 of both types are closed, and the third n-type transistor 6 is open and provides the voltage transfer from the output 9 of the element AND-NOT 1 to the common point 13. Thus, the gates of the first transistors 2 and 4 of both types receive a logical signal from the output 9 of the element AND-NOT, which depends on the information signal supplied to the first entrance 7 th terminal device.

If the information signal corresponds to logical 1, then the output 9 of the element AND-1 is the low voltage, the p-type transistor 2 is open, and the p-type transistor 4 is closed. At the output terminal 12 of the device, there is also a high level signal. I

Thus, an element with three states is functioning when using only two input actions, and the input terminals of the device are connected only to the gates of the MDM transistors. Compared with the known device, this device has one or more terminals for its realization, one transistor less, if an additional inverter is used in the known device to obtain an additional control signal.

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It is not a common bus, which differs from the fact that, for the sake of simplicity, a third n-type transistor is inserted in it, the drain of which is connected to the output of the H-NOT element, the source is connected to the drain of the second n-type transistor, and creative - with one of the input terminals of the device and with the gate of the second tran

An element with three states on a CMDF transistor containing an NAND element, two p-type transistors, the first and second n-type transistors, the inputs of the AND-N element are the input terminals of the device, and the output is connected to the gate of the first trans - Q is a p-type resistor, the source of which is a p-type resistor, the source of which is connected to the power spike, and the drain is connected to the gate of the second transistor of the n-type and to the additional output of the NAND element, which is a common point Which serially connected transistors of this element.

it with the power bus, and the drain with the output terminal of the device and with the drain of the first n-type transistor, the source of which is connected to the common bus, and the gate to the drain of the second n-type transistor, the source of which is also connected1492467

It is not a common bus, which differs from the fact that, for the sake of simplicity, a third n-type transistor is inserted in it, the drain of which is connected to the output of the H-NOT element, the source is connected to the drain of the second n-type transistor, and the gate - from one of the input terminals of the device and to the gate of the second p-type transistor, the source of which is connected to the supply spike, and the drain is connected to the gate of the second transistor of the p-type and to the additional output of the NAND element, which is a common point series-connected transistors of the same name.

Claims (1)

Formula and ebreg and An element with three states on KMDP transistors containing an AND-NOT element, two p-type transistors, first and second p-type transistors, the inputs of the AND-element being the input terminals of the device, and the output connected to the gate of the first p-type transistor whose source is connected to the power bus, and the drain to the output terminal of the device and to the drain of the first η-type transistor, the source of which is connected to the common bus, and the gate to the drain of the second η-type transistor, the source of which is also connected 1492467 ⁶ I. nen with a common bus, characterized in that, for the sake of simplification, a third η-type transistor is introduced into it, the drain of which is connected to the output of the NAND element, the source is connected to the drain of the second η-type transistor, and the gate is connected to one from the input terminals of the device and with the gate of the second p-type transistor, the source of which is connected to the power bus, and the drain is connected to the gate of the second η-type transistor and with the additional output of the AND-NOT element, which is a common point of series-connected transistors of the same name .