SU1714807A1 - Nonbinary synchronous counter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in electronic devices of digital technology for processing discrete, information in the conditions of interference. The counter contains elements AND 3 and 8. elements OR 5 and 9, triggers 4.6.7,10 and element OR-AND 11. The counter can have a conversion factor of not only 11. but 2 "" + 2 "- 1, where m is The bit size of the binary counter, n is the bit size of the bits not blocked from the output of the bit shift, moreover, t > & n. 1 ill.

Description

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The invention relates to digital technology and is intended for use in discrete information processing devices with enhanced noise immunity.

The aim of the invention is to increase the noise immunity by blocking the triggers of those bits that are redundant for a given counting module of a non-traditional synchronous counter,

The drawing shows a non-binary synchronous counter, a specific variant,

In the drawing, the following notation is accepted: input bus 1, binary synchronous counter 2, which includes element 3, trigger 4 low-order bit, decoder (element OR) 5, triggers 6 and 7 high-order bits outside which the decoder contains element I) 8, element OR 9, trigger 10 bits of the signal, the decoder (element OR-AND) 11.

The inputs of the decoder 8 are connected to the direct outputs of the trigger 4, 6 and 7 bits of the binary synchronous counter 2, the clock input of which is connected to the input bus 1 and the clock input of the shift shift trigger (D-trigger) 10, the inverse output of which is connected to the input installation of the zero trigger trigger 7, the first input of the decoder 11 is connected to the forward output of the trigger 10 of the shift offset and the first input of the AND 3 element, the information input of the D-trigger 10 of the shift offset is connected to the output of the OR 9 element, whose inputs are connected respectively to exit decoder 8 and the output of the decoder 11, the remaining (second and third) inputs of which are connected respectively to the direct output of the trigger 4 low and the inverse output of the high priority trigger b, the direct output of which is connected to the second input of the I 3 element whose output is connected The input of the decoder 5 and the reset input of the trigger 4 low-order, the direct output of which is connected to another input of the decoder 5.5 output of the decoder 5 is connected to the input of the resolution resolution of the first trigger 6 high bits. The input of the resolution trigger of the low 4 bit trigger is a logical 1 signal.

The decoder 5 serves to detect the code at the low-order outputs of binary counter 2 and the output of the AND 3 element.

The decoder 8 serves to detect the transfer signal, i.e. code 111 at outputs Q1, Q2 and Q3, respectively, bits 4, 6 and 7.

The decoder 11 is used to detect the code 1XX1 or XOX1, respectively, at the outputs Q1-Q4 of bits 4, 6 and 7 of the trigger 10,

In the initial state, since the installation circuits are not shown, the counter may be in any of the eleven possible states. Let the counter be in the state when the direct outputs Q1-Q4, respectively, of bits 4, 6, 7, and 10, have the code 0000. In this case, the outputs of the elements AND 8 and OR-AND 11 will be zero, therefore the output of the element OR 9 will also be zero.

With a clock pulse, binary counter 2 operates until its code 111, t, e, units, is generated at its outputs.

at the direct outputs of bits 4, b and 7, and at the output of the D-flip-flop 10 Q4 will be zero, so that the code 1110 is formed, therefore at the output of the element And 3 by this time will be zero, and the counter has eight states.

With the supply of the eighth input pulse, binary counter 2 is nullified, and since the unit potential was formed through AND 8 and OR 9, the D-flip-flop 10 goes into one state and a code 0001 is formed. At the inverse output of D-flip-flop 10 the zero potential that blocks in the zero state the trigger 7 bits of binary counter 2, and the output of the decoder 11 will be

unit,

When the ninth input pulse is fed through bus 1, the first bit 4 of binary counter 2 goes back to the unit state, such that code 1001 is formed, therefore

The output of the decoder 11 remains one. With the feeding of the ninth input pulse on bus 1, the trigger 4 of the first bit goes to zero, and because of the presence in the previous clock of the unit at the output of the decoder 5

trigger b occupies a single state, such that code 0101 is formed. Consequently, at the output of decoders 8 and 11, a zero is formed, which through the OR 9 element prepares to trigger a D-flip-flop 10.

at the output of the element 3, a unit is formed which blocks the trigger 4 bits of the binary counter 2 along the input of the installation to zero and prepares the trigger 6 bits for the subsequent triggering, since the output of the decoder 5 remains one.

With the supply of the eleventh input pulse on bus 1, the counter returns to the initial state, as the code 0000 is generated.

Thus, the counter counts up to eleven in a uniform binary code.

Claims (1)

In this case, a nonbinary synchronous counter is built with a recalculation factor of 2 + 2 1. In the most general case, a counter can be constructed with a recalculation coefficient of 2 + 2 -1, where m is the binary counter; n is the non-blocking bit from the inverse output of the bit shift trigger; I is a number that is less than the conversion factor of the counter formed by the lower-order triggers and determined also by the number of triggers of this counter, blocked from the output of the element I 3 at the installation input to zero, and n and I. Technical and economic efficiency of the proposed counter by Compared with the known one, it is to preserve the possibility of not falling into an excess state at any conversion factor determined by the general case, which is very important in the conditions of interference. The invention includes a non-binary synchronous counter containing a group of low and high bit triggers, a shift shift trigger, two decoders and an OR element whose output is connected to the shift-shift D input of the shift switch, the inputs of the OR element are connected to the outputs of the first and second decoders, clock the inputs of the trigger low and high bits and the shift shift trigger are connected to the input bus; the inputs of the first decoder are connected to the outputs of the lower trigger bits and high bit triggers; the forward output of the shift shift trigger is connected to the first the second decoder inputs, the remaining inputs of the second decoder are connected to the corresponding outputs of the lower and higher order triggers, the outputs of the lower order trigger are connected to the resolution enable inputs of the next lower order trigger, and the inverse shift shift trigger output is connected to the reset input of subsequent higher bit triggers, characterized in that, in order to increase noise immunity, in A third decoder and element I are entered, the output of the third decoder is connected to the counting input input of the first trigger of the higher bits, and the inputs of the third decoder are connected to the corresponding outputs of the lower trigger and the output of the And element, which is connected to the reset input of one or more lower trigger and the inputs of the And element are connected to the direct output of the shift discharge trigger and the direct outputs of the higher-order flip-flops, which are not blocked by the reset input from the output of the shift shift trigger.