SU1714590A1 - Device for adding numbers with variable base of number system - Google Patents

Abstract

The invention relates to computing and can be used in digital accumulators, dividers with a variable division factor, as well as the formation of discrete | frequency grid. The purpose of the invention is: simplification of the device. A device for adding numbers with a variable base of a number system contains n first- and out combinational adders 1, n switches 2, n groups of four elements AND 3, n second combinational adders L, n registers 5, information bus 6, module control bus 7, input number selection system 8, clock input 9 and output bus 10, which are functionally interconnected. 1 il. • 'u ^^ ate you o

Description

The invention relates to computing and can be used in digital accumulators, dividers with a variable division factor j as well as to form a discrete frequency grid.

It is known a device whose composition includes three registers of a code switch, a trigger, a clock pulse generator, an OR element, and an accumulator.

The disadvantage of this device is the impossibility of its functioning in the binary-decimal number system. .

Closest to the proposed

The device is a device that contains two combination adders, a multiplexer, a switch, a trigger and a register, bit outputs of O f oTOporo, respectively, connected to the information inputs of the first group of the first adder and the output bus of the device, each clock cycle of the register of each tetrad is connected to a clock input the device and, accordingly, with the installation entrance of the rigger, a single input of which each tetrad is connected to the output; transferring the first adder, the bit outputs of which are connected respectively to the information inputs of the register, the information inputs of the second group of the first adder of each tetrad are connected to the bit outputs of the multiplexer, the information inputs of the first group of which are connected respectively to the information bus of the device and to the information inputs of the first group of the second adder ,, the information inputs of the second group of which are connected respectively to the bus with the control bus of the device module, and the bit outputs are connected to the second the adder of each tetrade is connected to the information inputs of the second multiplexer group, the control input of which is connected to the switch output of each tetrade, the control inputs of the coder of each tetryd are connected to the input of the device number selection, the first information input of the switch of each tetrad is connected to the output of the corresponding trigger, the second information inputs of the switches in all tetrads are connected to the trigger output of the highest one (the nth tetrad, and the transfer outputs of the first and second combinational the adders of the i-th tetrad (where i 1,2, ...,) are connected respectively to the transfer inputs of the (1h-1) -th tetrad.

This device can function both in binary and binary-decimal number systems, however its disadvantage is excessive complexity.

The purpose of the invention is to simplify the device.

The goal is achieved by

5 that in a device for adding numbers with a variable base of a number system, containing in each tetrad a switch, a register and the first and second combinational adders, and

0 bit outputs of the first combinational adder are connected respectively to the information inputs of the register, the clock input of which is connected to the clock input of the device,

5 whose output bus is connected to the register bit outputs in each tetrad, the information inputs of the first group of the second adder of each tetrad are connected respectively

0 with the information bus of the device, the input for selecting the number system of which is connected to the control input of the switch in each tetrad, the transfer outputs of the first and second combinational adders of the i-th tetrad (where i 1,2, .o, p-1) are connected respectively to the transfer of the (1 + 1) -th tetrad, additionally in each of its tetrads a group of four is introduced

0 elements AND, the first inputs of which are connected respectively to the bits of the control bus of the device module, the output of the switch of each tetrad is connected to the second inputs of the elements

Claims (1)

5 And the groups, the outputs of which are connected respectively to the information inputs of the first group of the first combinational adder, the information inputs of the second group of which are connected respectively to the bit outputs of the second combinational adder. The information inputs of the second group of the latter are connected to the bit outputs of the register, the transfer output of the second combinational adder in each tetrad is connected to the first information input of the switch, the second information inputs of which in all tetrad are connected to the transfer output of the second combinational adder of the nth tetrado The essence of the invention is that the introduction of a group of elements And the establishment of new connections allows you to organize the process of adding numbers with a variable base system we are counting without using the group of multiplexers and the group of triggers. In comparison with the known, the proposed device is characterized by the presence of new elements: groups of elements AND in each of the tetrad devices of the device with their connections to the switch, the first adder and the device control bus, and between adders, register and switches in each of the tetrads of the device. The drawing shows a block diagram of the device for adding numbers with a variable base of the number system. The device consists of -1c adders, 2-2f switches, groups 3i-3p of AND elements, combinational adders 4, registers, information bus 6, module control bus 7, input 8. number system selection, clock input 9 and output bus 10. The device works in the following way . In the binary number system, the signal O is supplied to the input 8 of the device. In this case, the switches 2 -2 pass to their outputs a signal arriving at their second information input from the transfer output of the adder .1y and block the signals arriving at their first information input, from the transfer outputs of the remaining adders 1 „-1lm The signals at the transfer outputs of the combinational adders 1 -1 and t / i p are potential and therefore can change their logic level only after the next clock pulse arrives at device 9 . The input 6 of the device is present in the binary parallel code C n-bit input number A, which is divided into n groups of four bits and fed to the corresponding information inputs of the first groups of adders -If, and the lower bits of the number A are fed to the corresponding inputs adder To the input 1 06 7 of the device is supplied in parallel binary code k is an n-bit number P 2 -M, where M is the modulus value. The number P is also divided into n groups of four binary bits and enters the information inputs of groups 3 3 elements AND, the lower digits of the number P being given n, and the corresponding inputs of group 3 elements I. Let the output of the transfer If adder present a logical level This level through the switches 2 /, -2f, is fed to the control inputs of all groups 3, -3 elements AND, which at the same time ... closes and the zero value of the binary codes from their outputs is fed to the information inputs of the first group of adders 4 p. this output code su mmators - is equal to the code on in-. formation inputs of their second groups, i.e. "code on the discharge outputs of adders 1 n. Thus, if there is a logical level O at the output of the transfer of adder 1, the combination adders C -1" and the registers 5 5f) form a single pn-bit binary accumulating adder, the process of incrementing information in which the value of the input number A occurs synchronously with the arrival of clock pulses at the clock inputs of the registers 5-5p. When the number S in registers 5) 1-5 is reached, at which the condition S + Ab2 is fulfilled, the output of the transfer of adder 1 is a level, logical 1, which through the switches 2 -2 is fed to the control inputs of all groups 3 elements and the latter open at the same time, skipping the information inputs of the first group of adders k -k number Po With the arrival of the next clock pulse at the device input 9 to the contents of the registers 5 5 (the number A + P is added, after that the output of the 1rt transfer output is set logical level Oh, gr The unit 3 closes the elements and closes and resumes the process of filling the register capacity of 5-5c with a CONSTANT increment equal to the number of AOs. This process continues until the next content overflows, totalizers 1/1 -1pt, e, until the level of logical 1 At the output of the adder 1 is about 7. 1 Thus, the average frequency of the binary accumulator is equal to A f A t M where f is the clock frequency. In the binary-decimal number system, a signal is sent to the input 8 of the device. 2n skig to their outlets The inputs coming to their first information inputs, from the transfer outputs of the corresponding adders 1 to 1, and blocking the signal coming to their second information inputs from the transfer output of the adder 1, the input 6 of the device are fed in parallel to the sixth code; significant decimal number A which is every ten days received at the information inputs of the first group of adders 1 -If. At the module control input 7, in the parallel binary-decimal code, n values of the decimal number 6 are written, which arrive at the information e 31 input groups) -3 VI elements. If the output of the transfer of the adder 1; (i 1, .. n) there is a logical O level, then the corresponding group of 3j elements of I. is closed. At the same time, the information inputs of the first group of adder k receive a zero value of the discharge code and, therefore, the number at the output of the adder: - | equal to the value of the number. on the information inputs of its second group. Thus, if there is a logic level O at the output of the transfer of the adder t, the latter, together with the register 5, decodes the A-bit binary accumulating c.matmator, the information increment process in which the value of the corresponding decade of A numbers) occurs synchronously with the arrival of pulses at the clock input of the 9th device. If after the arrival of the next so tovy pulse at the output of the transfer of the adder 1; the logical level 1 is set, then the corresponding group 3 is opened; the elements And and the code of the number 6 is fed to the information inputs of the first group of the adder. The next pulse arriving at the clock input of the register 08 5; causes the addition of the sum of the corresponding decade of the number A (including the transfer of the number A from the previous decade) with the number 6 ". Thus, at the outputs of each of the information varies from 6 to 15, which is equivalent to the operation of cascades of the decimal storage in the range from O to 9. The device module, when operating in the binary-decimal number system, is equal to 10, i.e. determined by the number of this module of each of Ascad is 10. The proposed device is identical in functionality to a known device, however, it is much simpler, because by introducing groups of elements AND and establishing new connections, the group of multiplexers and the group of triggers are excluded. one and the same number of bits), since the latter is its constituent part The invention A device for adding numbers with a variable base of a number system containing The switch, the register and the first and second combinational adders are also located; the first group of the second combinational adder of each tetrad is connected respectively to the information bus of the device, the input of the selection of the number system of which is connected to channeling yuschim input switch in each tetrad, transfer outputs of the first and second adders combinational tetrad i-th (wherein i 1,2, O..P-1) are respectively connected to transfer inputs. (1 + 1) -th tetrad, characterized in that, in order to simplify the device, a group of four elements is introduced into each of its tetrads. And, the first inputs of which are connected respectively to the bits of the control bus of the device module, the output of the switch of each tetrad is connected to the second inputs of elements AND of the group whose outputs are connected respectively to the information inputs of the first group of the first combinational adder, the information inputs of the second group of which are connected respectively to the discharge outputs the second combination adder, the information inputs of the second group of which are connected respectively to the bit outputs of the register, the output is transferred sa second adder combination in each tetrad connected to a first data input switch, the second data inputs are all tetrads connected to the output of the second transfer koibinatsionnogo adder nth tetrads.