SU1706026A1 - Former of difference frequency of pulse signals - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for generating and processing information. The purpose of the invention is to increase reliability. The device contains keys 1, 2 and 6 with the memory of the control signal, triggers 3 and 4, element 5, input buses 8 and 9, bus 10 clock pulses and output buses 11-13. The introduction of trigger 7 and the organization of a new set of inter-element links eliminate errors in the subtraction of pulse signals when pulses arrive at the input buses during the formation of a lower frequency pulse, 3 sludge.

Description

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The invention relates to a pulse technique and can be used in a device for forming and processing information.

A device for generating differential frequencies of pulse signals is known, which contains three keys with a control signal memorization, two triggers with a counting input, an And element, two input buses, a clock bus, and three output buses.

A disadvantage of the known device is low reliability of operation. If the pulse of one of the subtracted frequencies (or the pulses of both subtracted frequencies simultaneously) arrives at the corresponding input bus during the formation of a lower frequency pulse at the device output, then errors in the subtraction of the pulse signals are inevitable in the device operation.

The closest to the present invention is a device for generating differential frequencies of pulse signals, comprising first and second keys with a control signal, whose information inputs are connected to the first and second input buses, respectively; the first outputs are connected to the counting inputs of the first and second triggers, respectively the second outputs are connected respectively to the first and second output buses, the control inputs are connected to the direct outputs of the first and second triggers, respectively, the R-inputs of which x connected to the output of AND gate having a first input connected to the third output line and the output of the third switch latched control signal, an information input of which is connected to the bus clock.

A disadvantage of the known device is low reliability of operation. If the pulse of one of the subtracted frequencies (or the pulses of both subtracted frequencies simultaneously) arrives at the corresponding input bus during the formation of a lower frequency pulse at the device output, then errors in the subtraction of the pulse signals are inevitable in the device operation.

The purpose of the invention is to increase reliability by eliminating errors in the subtraction of pulsed signals when pulses arrive at the input buses during the formation of an output pulse of lower frequency.

The goal is achieved by the fact that the device for generating differential frequencies of pulse signals, containing

the first and second keys with the control signal memorization, whose information inputs are connected respectively to the first and second input buses, the first outputs are connected to the counting inputs of the first and second triggers, respectively, the second outputs are connected to the first and second output buses, respectively, the control inputs are connected to

0 direct outputs of the first and second triggers, respectively, the R inputs of which are connected to the output of the element I, the first input of which is connected to the third output bus and the output of the third key with

5 by storing the control signal, whose information input is connected to the clock pulse bus, a third trigger is entered, the first and second S inputs of which are connected to the direct outputs of the first and second triggers, respectively, the direct output is connected to the control input of the third key with the control signal memorized , R-input and inverse output are connected respectively with the first and second inputs

5 elements I.

In order to clarify the possibility of achieving the desired positive effect of the device, expressed by the aim of the invention, it is necessary to consider the functioning of the prototype and the claimed device in the same situations.

Let the bus 7 in the prototype receive impulses 1, 3, 4, 6, 7 and 11, and the bus 8 - impulses 2. 5. 8, 9, 10, 12 and 13 (fmg.1). After

5, the action of the pulse front 5 on the bus 12 begins the formation of a pulse 6 of a lower frequency and through the element I there is a reset to the O flip-flops 1 and 2 (pulse slices 14 and 15). The level O formed as a result of this at the output of the OR element closes the AND element, which terminates the effect of the reset pulse on the R inputs of the triggers 1 and 2. Since at the control input of the key 3 there is a level O, the pulse 6. arriving at the bus 7 after resetting the flip-flops 1 and 2. but during the action of the pulse 12 on the bus 16, passes to the first output of the key 3 and sets to 1 by counting trigger input 1.

0 at the output of which the front of the pulse 17 is formed. Level 1 from the output of the trigger 1 enters through the OR element to the second input of the element I. Because at this time the first input of the AND element has an 5 pulse 16, a pulse is generated at its output that ensures a reset to O trigger 1, which causes a pulse 17 to form at the output of the last slice. Thus, at the time of slice 6 forming on bus 7, trigger 1 is in

0y state, i.e. information about the pulse b in the device is not registered. This entails an incorrect device processing of the pulse 7 and, therefore, an error in the subtraction of the pulse signals, as a result of which the pulse 7 on the bus 10 is not isolated. Similarly, an error occurs in the operation of the device in the subtraction of the pulse signals when it processes pulses 11 and 12, as a result of which pulse 13 on bus 11 is also not singled out. From this it follows that the prototype has a low reliability of operation when pulses arrive at the input buses during the formation of an output pulse of lower frequency.

When considering the timing diagrams of the proposed device in the same situations (Fig. 3), it is clear that they in both cases produce an error-free subtraction of the pulsed signals, as a result of which the pulses and 40, t are allocated on its first and second output buses, respectively. e. The proposed device has a high reliability of operation when pulses arrive at the input buses during the formation of an output pulse of lower frequency.

Thus, the introduction of a third trigger into the device and the organization of a new set of inter-element links eliminate the errors in the subtraction of pulse signals when pulses arrive at the input buses during the formation of a lower frequency pulse. This increases the reliability of the proposed device in comparison with the prototype.

FIG. Figure 1 shows timing diagrams explaining the operation of the prototype and the process of the occurrence of errors when it subtracts pulsed signals; 2 is an electrical functional diagram of the device proposed; FIG. 3 shows timing diagrams explaining his work.

The device for generating differential frequency pulsed signals contains the first 1 and second 2 keys with the control signal memorization and the first and second triggers 3 and 4, the element 5, the third key 6 with the control signal memorization, the third trigger 7, the first and second inputs tires 8 and 9, bus 10 clock pulses, the first - the third output bus 11-13.

The information inputs of keys 1 and 2 are connected respectively to buses 8 and 9, the first outputs are connected to counting inputs, respectively, of triggers 3 and 4, the second outputs are connected respectively to buses 11 and 12, control inputs are connected to direct outputs, respectively, of triggers 3 and 4, R- the inputs of which are connected to the output of the element And 5, the first input of which is connected to the R input of the trigger 7,

bus 13 and the output of the key 6, the information input of which is connected to the bus 10, the control input is connected to the direct output of the trigger 7, the inverse output of which is connected to the second input of the element 5, and

0, the first and second S-inputs are connected to direct outputs, respectively, of the flip-flops 3 and 4.

The device works as follows.

5B in the initial state, the triggers 3 and 4 are set to O, the buses 8 and 9 do not receive pulses, the bus 10 receives clock pulses of stable frequency and duration, and on buses 11 and 12 they act

0 levels O. Since in this mode at the control input of the key 6 there is a level 1, then the clock pulses at the output of the key 6 do not pass and the bus 13 has the level O, and the inverse output of the trigger 7

5 level 1.

The pulses 14 and 15, arriving simultaneously on the tires 8 and 9 (Fig. 3a, b), are transmitted to the first outputs of the keys 1 and 2 and set the triggers 3 and 4 to the state

0 1. At the same time, at the outputs of the triggers 3 and 4 (Fig. 3 d, e), the fronts of the pulses 16 and 17 are formed, and at the direct output of the trigger 7 (Fig. Zg) and at the control input of the key b, the level O is formed. Clock pulse 18

5 (FIG. 3, c) is transmitted to the output of the key b, allocated on bus 13 (pulse 19, FIG. 13), switches trigger 7 to the O1 storage mode and, through element 5, (FIG. Ze), resets triggers 3 and 4 (pulse cuts 16 and 17).

0 This causes the trigger 7 to switch to state 1 and closes the O level with its inverse output (FIG. 3) element I 5. By the cut of the pulse 19 at the inverse output of the trigger 7, the level Y is set. By how many the forward output of trigger 3 is affected by the level O , then pulse 20 passes to the first output of key 1 and forms the pulse front 21 at the output of trigger 3, which causes translation of pulse 22 to the second

0 the output of the key 1 and the selection on the bus 11 pulse 23 (Fig.Zi). The pulse 24 passes from the bus 9 to the first output of the key 2 and forms at the output of the trigger 4 the front of the pulse 25, through which the forward output of the trigger

5 7, the O level is set. The clock pulse 26 is transmitted to the output of the key 6. At the same time, bus 27 is allocated pulse 27, trigger 7 is transferred to storage mode O, trigger 3 and 4 triggers are reset (pulse slices 21 and 25) and

Trigger 7 should be set to state 1. Under the action of pulse 28, which enters bus 8 after resetting triggers 3 and 4, but during pulse 13 acting on bus 13, pulse output 29 is formed at output of trigger 3. However, at the control input of switch 6 the level 1 continues to be maintained, since the trigger 7 is in the set 1 mode by the signal O from the direct output of the trigger 4. By the cut of the pulse 27 on the inverse output of the trigger 7 the level 1 is formed. Since the trigger 3 is in the state 1, the pulse 30 is transmitted from bus 8 to the second output of key 1 and you ate a bus 11, where it corresponds to the pulse 31. The pulse processing device 32 is manufactured similarly obrabotkeimpulsa 24 and complete formation of the bus 13 to pulse 33.

If the pulse frequency on bus 9 exceeds the pulse frequency on bus 8 (pulses 34–38), the device in this case is similar to the work of pulses 20, 22, 24, 28, 30, respectively, and leads to the release of pulses 39 and 40 on the bus 12 (FIG. 3K) and to the formation of a pulse 41 on the bus 13.

Each of the keys 1, 2, and 6, with the control signal memorized, can be performed in a known pattern.

The technical and economic advantage of the proposed device in comparison with the prototype is increased reliability of operation. This is due to. It can be noted that it excludes errors in the readout of pulse signals when pulses arrive at the input buses during

forming the output pulse of lower frequency.

Claims (1)

The invention The device for generating differential frequency pulse signals, containing the first and second keys with a control signal memorization, whose information inputs are connected to the first and second input buses, the first outputs are connected to the counting inputs of the first and second triggers, respectively. and with the second output buses, the control inputs are connected to the direct outputs of the first and second flip-flops, respectively, the R inputs of which are connected to the output element I, the first input of which is connected to the third output bus and with the output of the third key with the storage of the control signal, whose information input is connected to the clock pulse bus, characterized in that, in order to increase reliability by eliminating errors in the subtraction of the pulse signals upon receipt of pulses to the input buses during the formation of the output pulse of a lower frequency, a third trigger is inserted in it, the first and second S inputs of which are connected to the direct outputs of the first and second trigger respectively ov, the direct output is connected to the control input of the third key with the storage of the control signal, and the R input and inverse output are connected respectively to the first and second inputs of element I.