SU1374419A1 - Timer for multistage relay protection - Google Patents

Abstract

The invention relates to a pulse technique and can be used in the systems of automation, control and relay protection of power systems. The aim of the invention is to increase reliability. The time relay contains the starting organs 1, 2 and 3, the element OR-NOT 4, the binary summing counter 5, the elements AND 6, 7 and 8, the element OR 9, the RS flip-flop 10 and the pulse generator 11. When one or several starting organs are triggered the OR-NOT 4 element generates a logical zero at its output and enables the counter to be counted 5. Returning the starting organs to the initial state results in the appearance of a logical unit signal at the output of the OR-NOT 4 element, resetting the binary counter 5 and the RS flip-flop 10. Introduction in the device element OR NOT, RS-trigger and additional And the second element of the proposed scheme and its compound achieves this goal. 1 il. i (L

Description

with

four

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The invention relates to a pulse technique and can be used in the systems of automation, control and relay protection of power systems. The purpose of the invention is to increase reliability.

The drawing shows a functional diagram of the device.

The time relay contains the starting organs 1-3, the element OR-NOT 4, the binary summing counter 5, the elements AND 6-8, the element OR 9, the RS flip-flop 10, the generator 11 pulses.

The device works as follows.

At the initial moment of time, the starting organs are inoperable in the first state, and a signal of a logical unit is formed at the output of LHS-H 4. This signal, arriving at R-BXO of the d of counter 5 and trigger 10, zeroed the counter and sets the trigger to zero regardless of the state of all other elements. Pulses with a frequency f from the pulse generator 11 are fed to the C input of the counter 5.

When one or several triggering bodies are triggered, the OR-NOT 4 element, forming a logical zero at its output, resolves the counting to count 5. The counting result is formed at the outputs Q, Q ,, Q is the logical unit that appears in the counting process de, arrives at the input of one of the elements And, at the second input of which a logical unit has already arrived from the starting organ. For example, when triggered start-up unit 2, after a unit appears at the output of counter 5, logical units are frmmed at both inputs of element 7. At the same time, a logical signal is received at the S input of the RS flip-flop 10 from the output of the element OR 9

units, sets the trigger to one. According to the known frequency of the pulse generator fp, the required time t. defined by the expression

 d;

where clj.- is the dividing ratio of the counter at the output; (, 2,3).

ka on exits Q ,, Q, Q

Similarly, the time relay works when any other triggering organ is triggered.

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For definiteness, the sensitivity of the trigger organs, for example, the most sensitive trigger organ 3, will be set and the sensitivity decreases with decreasing number. At the same time, the delayed time (ki, formed at the outputs of the logic elements And 6-8, have the following relationship:, .t .. In case of failure of one of the starting organs, its operation is reserved by the triggering organ next in sensitivity .. So, if the triggering organ fails 2 then its triggering is reserved by a more sensitive organ 3, forming a logical unit signal at the output of flip-flop 10 with a time delay tj. Returning the trigger organs to the initial state results in the appearance of a logical unit signal at the output of the OR-NOT 4 element, i.e. reset d oichnogo counter 5 and the RS-flip-flop 10. Thus, the introduction of the element I-UIH-HE, RS-flip-flop, and additional elements and their compounds in accordance with the circuit form; loi invention allows to increase reliability of the device.

Claims (1)

Invention Formula Time relay for multistage relay protection, containing start-up organs with different trigger settings, pulse generator, pulse counter, connected to the first inputs (n-1) of the And elements, whose second inputs are connected to the outputs of the corresponding starting organs, the OR, with its (p-1) inputs subconnected to the outputs (p-1) elements. Item 5 is characterized in that, in order to increase reliability, an OR-NOT element, an RS flip-flop and an additional nth AND element are introduced, and the counter is designed as a binary summing counter, the C-input of the counter being connected to the output of the pulse generator, The R input of the counter is to the output of an OR-NOT element whose inputs are connected to the inputs of n-starting organs, the nth element and the inputs are connected to the output of the nth starting element and the nth output of the binary summing counter, RS flip-flop 8-input connected to the output of the element OR, R-input - to the output of the element LEE-NO, and the output is a trigger output time switches.