SU1698843A1 - Electric wiring tester - Google Patents

Abstract

The invention relates to a control and measuring technique. The purpose of the invention is to increase the functionality and increase the reliability and performance of the control - to - / --- is achieved by operatively programmable providing the necessary and sufficient control of the test object with any number of mounting points from the set of control devices implemented. The device contains a switching unit 18 for the test object, the first 12 and the second 16 status indicators are monitored. my connection, the first element 11 of equilibrium, the first 4 and second 22 account

Description

The invention relates to the instrumentation technology and can be used to monitor electrical connections and the operability of switching devices. The goal is to enhance the functionality, increase reliability and speed of control.

On this 1 is a block diagram of an electrical installation control device; figure 2 is a functional diagram of the launch unit; fig. 3 - the same, the first (second) control unit; 4 and 5 show the same, first and second switches, respectively; 4) 6 and 7 - the same, multiplexer blocks and decoders, respectively; FIG. 3 is a functional diagram of a digital memory array; Fig. 9 is a functional block diagram for setting modes; in FIGS, the same, of the first (second) block of the task of checking programs; on the same first (second) survey counter; FIG. 12 is the same, the communication number control unit in FIGS. 13 and 14 are the functional diagrams of the result control indicator and the second (first) link state indicator, respectively; on Fig - the data bus of the decoder unit, as well as its connection to the blocks of multiplexers, switching and decoders in accordance with figure 1 about

A device for controlling electrical installation (FIGS. 1) (UKEM) contains a series-connected clock pulse generator 1, the first element AND 2, the second equivalence element 3, the first interrogation counter 4 and the first control unit 5 The device also contains a device start-up unit 6, the first output control which is connected to the second input of the first element And 2, the second,

the control output is connected to the second input of the second equivalence element 3, multiplexer unit 7, the power input of which is parallel connected to the second power output bus of the first switch 8, the first power output of which is connected in parallel to the power input bus of the first control unit 5, the enable input is connected to the fourth output control unit 6 start the device, and the control input is connected in parallel with the control output bus of the first control unit 5, whose address output is connected in parallel with the bus of the second ad The common input of the first test program setting unit 9, the first address input of which is connected in parallel to the address output bus of the first poll counter 4 and the address input of the multiplexer unit 7, the mode setting unit 10, the information input of which is connected in parallel with the first input of the first equivalence element 11, the first input the monitored communication state indicator 12, the information output of the multiplexer unit 7 and the first input of the communication number control unit 13, the third input of which is in parallel connected to the information the output of the mode setting unit 10 and the second input of the second element AND 14, the second input in parallel is connected to the second input of the first equivalence element 11, the digital memory matrix 15 output and the input of the second indicator of the monitored communication state 16, the control output is connected to the input of indicator 17 monitoring the result, and the address output bus is connected in parallel to the third address input of the digital memory matrix 15, the first address input of which is connected in parallel with the address output bus of the first block 9 of the verification program, and the first and second control inputs are connected to the first and second control outputs, respectively (branch 9, mode setting unit 10, switching unit 18 of the test object, whose input is connected in parallel with the information input unit

30 - 33, control buttons 34 - 37, & also logic elements 38 - 41. When the Start button 34 is pressed, all the counters of the device for controlling electrical installation are reset (in Fig. 1, no communications are indicated) by the signal from the output of the And 39 element. At the same time

7 multiplexers and a dan-jq output bus outlets of the first latch trigger of the decryptor unit 19, the power input of which is connected in parallel to the second power output bus of the second switch 20, the first power output of which is connected in parallel to the power input bus of the second control unit 21, the enable input is connected in parallel with the turn on input of the first control unit 5 and the turn on output of the first switch 8, the control output 20 is connected in parallel with the control input bus of the second switch 20, and the second control input It is connected to the information output of the second polling counter 22, 25 whose address output is parallel connected to the address input bus of the decoder unit 19 and the first address input of the second test program setting unit 23, the address input of which is connected in parallel to the second digital matrix address input bus 15 memory, the second address input is connected in parallel with the address output bus of the second control unit 21, and the control output is connected in parallel with the input of the unit 6 to start the device, the first control input is second the control unit 21 and the control input of the second polling counter 22, whose information input is connected to the output of the third equivalence element 24, the second input of which is connected to the third output of the device start block 6 f, and the first input is connected in parallel to the control input of the first polling counter 4, the first input control of the first control unit 5 and the control output of the first test program setting unit 9, the output of the first equivalence element 11 is connected to the fifth input of the second element I 14, the output of which is connected to the third input of the first element and 20

Unit 6 device startup (fig „2} contains resistors 25 - 29, providing a high-level input current of logic elements (triggers)

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The signals are: control output, allowing the passage of clock pulses to the input of the first poll 4 counter and the control output, ensuring the inclusion of the first 5 and second 21 control blocks using the first switch 8 (FIG. 1). The counting of the first poll 4 poll is performed. from the moment the button 34 is released and the signal is removed from the output of element 39. Upon completion of the check, the input of element 38 receives a high level signal, which sets the first 31 flip-flop to the initial state. The second 32 and third 33 triggers, control buttons 35 - 37, as well as elements 40 and 41 serve to pre-set the number of the individual or initial tested connection. From the control output of the element 40, the second poll counter 22 is preset, and from the control output element 41 is presetting the first counter 4 polls using the control buttons 37 and 36, respectively. The second trigger 32 and the control button 35 serve to organize the pulses of the installation of the first 4 and second 22 polling counters, while the control output shifts by one address and continues the test mode of the device after registering the erroneous connection of the test object.

The control unit 5 (21) (FIG. 3) is made according to a single schematic diagram, but has connections in accordance with FIG. 1 and contains counters 42.1 - 42.M controls, decoders 43.1 - 43.N controls o The number M denotes number of control levels; the number N is the number of control decoders included in the control unit 5 (21), where N is defined as

(

where n is the binary input

control decoder code;

0 5 o

five

0

five

0

five

The signals are: control output, allowing the passage of clock pulses to the input of the first poll 4 counter and the control output, ensuring the inclusion of the first 5 and second 21 control blocks using the first switch 8 (FIG. 1). The counting of the first poll 4 poll is performed. from the moment the button 34 is released and the signal is removed from the output of element 39. Upon completion of the check, the input of element 38 receives a high level signal, which sets the first 31 flip-flop to the initial state. The second 32 and third 33 triggers, control buttons 35 - 37, as well as elements 40 and 41 serve to pre-set the number of the individual or initial tested connection. From the control output of the element 40, the second poll 22 is preset, and from the control output 41 preset the first counter 4 polls using the control buttons 37 and 36, respectively. The second trigger 32 and the control button 35 serve to organize the pulses of the installation of the first 4 and second 22 polling counters, while the control output shifts by one address and continues the test mode of the device after registering the erroneous connection of the test object.

The control unit 5 (21) (FIG. 3) is made according to a single schematic diagram, but has connections in accordance with FIG. 1 and contains counters 42.1 - 42.M controls, decoders 43.1 - 43.N controls o The number M denotes number of control levels; the number N is the number of control decoders included in the control unit 5 (21), where N is defined as

(

where n is the binary input

control decoder code;

ha - the order number of the control level ,,

The total number of address outputs is defined as A pM, and the total number of control outputs:

"Nm

Bunp S 2 "G y-1

With the arrival of the signal at the input of the input, the 4341–43 element is connected to the power bus of the element and, consequently, the power is connected to one of the control decoders (43.2 - 43.1) of each control level (42 „1–42, M). The decoders are connected in sequence after testing 2 control outputs, starting from the senior M. The total number of power inputs is determined by B, WT Bynp K, - where K is the number of power inputs of block 7

The decoder block 19 (Fig. 7) contains 49.1 - 49. It is decoder and is controlled via the address input bus from the second polling counter 22, and the same one via the power input bus from the second switch 20. The outputs of the elements 49.1 - 49. K are connected to the corresponding inputs unit 7 multiplexer and switching unit 18 of the test object at a certain time only at one output of the K-th element there is a low signal level, since only one of the K elements of block 19 at a certain point in time is turned on. Alternately checking for low signal levels with

multiplexers (block 19 decoder 25 using block 7 multiplexers on

ditch). The first control input is the setup input, and the second control input is the counting input for the 42.1-42. M control counters,

The first switch 8 (Fig. 4) contains cells 44.1 - 44, N and 45.1.1 - 45. To the switching unit, employees 4to convert the control signals of the first control unit 5 to the supply voltage, while the switching cells 44, 1 44.N are used for the operation of the corresponding control decoders, and the switching cells 45.1 to 45. К for the inclusion of the corresponding elements of the multiplexer unit 7. The switch cell 44.1 is common to enable the first 5 and second 21 control blocks,

The second switch 20 (Fig. 5) is constructed similarly to the first switch 8 and contains 46.1-46.Ni cells and 47.1-47.K, but the switching-on cell of control blocks 5 and 21 is excluded. As switching elements in switches 8 and 20 used transistors KT361.

The multiplexer unit 7 (Fig. 6) contains 48.1 - 48.K multiplexers and is controlled via the address input bus

from the first polling counter 4, and via the input power bus from the first switch 8. At a certain time, one of the K elements is included in the operation, which allows you to combine

,, -

88438

thread outputs of all elements "Information inputs of elements 48" 1 - 48.K are connected to individual contacts of the switching unit 18 of the test object and the corresponding contacts of the elements of the decoder block 19

The decoder block 19 (Fig. 7) contains 49.1 - 49. It is decoder and is controlled by the address input bus from the second polling counter 22, as well as the power input bus from the second switch 20. The outputs of the elements 49.1 - 49. К are connected to the corresponding inputs of the unit 7 multiplexers and the switching unit 18 of the test object at the same time only a single output of the K-th element is present at a low signal level, since only one of the K elements of the block 19 is at a certain point in time included in the operation. Alternately checking for low signal levels with

five

,, - 0

50

55

All contacts check the test object as a whole and monitor the operability of the entire device.

The total number of information inputs of block 7 multiplexers and outputs of block 19 decoders is determined by

2i (AM)

as, and the total number of tested connections C, respectively.

The device uses the principle of a conditional logical unit as a positive factor, i.e. open input, when the blocks of 7 multiplexers and 19 decoders work together. Otherwise, each individual information input of the elements of the multiplexer unit 7 would need to be connected via a power bus limiting resistor.

Digital memory array 15 (Fig. 8) contains memory elements 50.1 - 50.1 and 51.1 - 51.i, equivalence elements 52 and 53, logic elements 54 - 56 OR. The mode of operation of the digital matrix 15 of the memory is set by the inputs 1 and 2 of the control from the block 10 setting the modes Record and Control In the Record mode, the information inputs of the memory elements 50 and 51 receive the binary code signals of the corresponding reference link addresses via the address input bus and are recorded address code on the signal

outdoor communication from block 7 multiplexers using block 10 set modes. In this way, a database of connections is formed corresponding to any individual subject under test. The address input receives the binary code of the communication serial number from the result control unit 13, which is generated by each individual link detected by the multiplexer unit 7. In the ECEM Control operation mode, the digital matrix of the memory 15 on the control inputs is transferred to the Read mode and compares the address codes of incoming address entries with the corresponding codes stored in elements 50 and 51. If the address codes of the detected communication do not match, the output of element 55 remains low level signal, stopping the process of control of the test object for error registration. The continuation of the control is carried out by pressing the control button | 35 of the unit 6 for starting the device after registering the erroneous communication.

The mode setting unit 10 (FIG. 9) contains limiting resistors 57 and 58, Record and Control buttons 59 and 60, respectively, RS flip-flop 61 and logic elements 62 and 63. When the button 59 is pressed, the Record at the second input of the logic element 62 is set a high level, and at the second input of the element 63 a low level of signals; With the appearance of a high level signal at the information input of the mode setting unit 10, the output of the element 62 appears high and the output of the element 63 has a low signal level, which corresponds to the recording mode information in the digital matrix 15 memory

ti. In the presence of a low level signal, a high logic level

At the information input and respectively at the low and high level at the control outputs of the mode setting unit 10, the digital memory matrix 15 is in the information storage mode. By pressing the Control button 60, a low signal level is set at the first control output, and a high level of the logic signal is established at the second control output, while, regardless of the external signals, the digital memory pattern 15 is in read mode. Information output block50

55

which, using pulse formers 73 and 74, sets the first polling counter 4 and the counters 42.1 to 42.M of the control (Lig.) of the first control unit 5 to the initial state, and the second polling counter 22 increases its output address code by one unit.

Similarly, the work of the second program setting unit 23 is performed, but the signal from its control output is both, stopping the end of the test of the test object by setting the start-up unit 6 to its initial state and turning off 15

20

t yjq e - 25

thirty

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69884310

Each mode setting 10 provides for blocking the mode stop. Recording a device on the second input of the second element I 14 at an independent value of the signal levels at the inputs and the output of the first equivalence element 11.

The first 9 and second 23 blocks of the verification program set contain limiting resistors 64 connected in parallel to the control buttons 65, the first 66 and second 67 trigger cells, whose outputs go to the first inputs of the first 68 and second 69 equivalent elements, respectively, whose outputs are connected to the first 70 and the second 71 elements OR, the outputs of which are connected to the first and second inputs, respectively, of the third element 72 OR, the inverse output of which is connected to the capacitor 73, the output of which is connected to the control output and block 9 (23) setting test programs and resistor 74. The first 66 and second 67 trigger cells contain n and rm, respectively, the number of RS flip-flops controlled by the corresponding button 65, providing at the output a binary code of the necessary and sufficient number of checked for any test object. If the set code matches the number of contact points corresponding to the object under test with the address code of the contact being checked at the address inputs, the outputs of the first 68 and second 69 equivalence elements produce a low logic level and accordingly a low level at the output of the first 70 and second 71 OR elements, with this at the output of the third element 72 OR a high logic level is generated,

which, using pulse formers 73 and 74, sets the first polling counter 4 and the counters 42.1 to 42.M of the control (Lig.) of the first control unit 5 to the initial state, and the second polling counter 22 increases its output address code by one unit.

Similarly, the work of the second program setting unit 23 is carried out, but the signal from its control output is the same, stopping the end of the test of the test object by setting the start-up unit 6 to its initial state and powering off the first 5 and second 21 control units, as well as 7 multiplexers and decoders nineteen.

The first 4 and second 22 polling counters (FIG. 11) are identical and each of them contains a binary counter 75.

Block 13 of the control of the number of communications (4mg. 12) contains the first 76 and second

77 address counters at the same time if JQ switch the switching of the transistor 93,

the number and sequence number of the tested connections corresponding to any object under test, the first matrix 78 of limiting resistors, the button 79 for setting the trigger cell code 80, 15 first 81 and second 82 equivalence schemes. first 83 and second 84 elements-1 you OR, logical elements 85 - 87, the first 88 and second 89 switches and the second matrix 90 of limiting 20 resistors, which ensure the operation of the first 88 and second 89 switches in the high impedance mode of the outputs. In the recording mode of the device, the check for correspondence of the number of connections corresponding to a given test object is carried out by comparing the code specified using the control buttons 79 and the trigger limit resistor 94 and the LED 95.

The circuit of the first 12 and second 16 state indicators (Fig. 14) is similar to the circuit of the control indicator 17 and differs only in the conductivity of the switching transistor.

The device works as follows.

Using the control buttons 65, the first 9 and second 23 blocks of the verification program set at the output of the trigger cells 66 and 67 of the binary code value corresponding to the total number of contact points to be checked for interconnection for this test object and the number of decoders (multiplex cells 80 with the final code of the second 30 ° C) of block 19 (7), receiving the address counter 77, the output code of which in this mode is the address output of the control block 13, the number of links. If the Record at the control output is correctly executed, the number of tested connections is 35

A roll of block 13 appears low. During operation of the device in the Monitoring mode, the end codes of the address counters 76 and 77 are compared with the set a priori known trigger point code 80, while the address output of the communication number control unit 13 is the first count code trigger cell 80, corresponding to the total number of the number of connections that determine the performance monitoring of the UKEM. Pressing the button 60 Control of the mode setting unit 10 sets the mode of the CCEM operation. At the same time, the outputs of the control box 10 determine the operation mode of the digits

ka 78 addresses. Only when 45 is equal in the memory of 5 memory, and the infor- matic key codes of the first 76, second 77 counters of the address and the trigger cell code 80 at the output of the control 13 of the block, a low signal appears, corresponding to a properly performed check. At input 3 of block 13, there is a low signal level in the Record mode and a high signal level in the Control mode, providing

The output of block 10 determines the mode of operation of the second element. And 1 by the second, input and block 13 of the control of the number of connections for the third link. When performing the specified operations and connecting the test object to the switching unit 18 (inputs-outputs connecting the test object n are indicated), pressing and releasing to ki 34. The unit for starting the device 6 starts the test. When the button 34 is started, the unit at the outputs of the elements 31 and 39 control signals are generated:

appropriate comparison of codes in the specified modes, and also controls the first 88 and second 89 switches for the source code of the address code for the digital matrix 15

memory Based on the foregoing, it follows that the unit 13 controlling the number of connections in the device performs four levels of control, ensuring high reliability of the test of the test object.

The control indicator 17 (FIG. 13) contains elements 91 and 92, providing a limiting resistor 94 and an LED 95.

The circuit of the first 12 and second 16 state indicators (Fig. 14) is similar to the circuit of the control indicator 17 and differs only in the conductivity of the switching transistor.

The device works as follows.

Using the control buttons 65, Penova 9 and the second 23 blocks of the verification program task are set at the output of the trigger cells 66 and 67 of the binary code value corresponding to the total number of contact points to be checked for interconnection for this test object and the number of decoders (multiplex when conducting this test for the performance monitoring of UKEM. Similarly, using the buttons 79 of the control unit 13

a binary code is established at the output of the trigger cell 80, corresponding to the total number of links determining the performance monitoring of the FEMC. Pressing the button 60 Control of the mode setting unit 10 sets the mode of the CCEM operation. The outputs of the control unit 10 determines the mode of operation of the digital memory of the 5th memory, and the information

The unit 10 output is determined by;. the operation mode of the second element. And 14 by the second, input and block 13 of the control of the number of links for the third time. After performing the above operations and connecting the test object to the switching unit 18 (the input-output connections of the test object are not indicated), pressing and releasing the button 34. The device start-up unit 6 starts the test. , Pressing the start button 34 of the block 6. At the outputs of the elements 31 and 39, the control signals are generated: from the first

the control output is a high level signal arriving at the second input of the first element I 2, which permits the passage of clock pulses that arrive at its first input from the output of the clock generator 1, which through the second equivalence element 3 arrive at the information input of the first poll counter 4, which when the button 34 is released, it is held in the zero state by a high level signal from the output of the element 39 to the control input (no connection is indicated in FIG. 1), from the fourth control output the low signal level stumbles to the input connection of the first switch 8 and using 44.1 cell produces switching power supply for output to decoders incorporating control 43.1. When releasing the Start button 34 of the device start block 6 and removing the high level of the control signal from the output of the element 39, the first poll counter 4 performs sequential switching of the information inputs of each, but at a certain moment, one of them 48.1 - 48. К, multiplexer of the block 7 and counters 42.1 - 42.M controls of the first control block 5, which in turn control the decoders 43.1 to 43.N, respectively. In this case, the decoders 43 sequentially through the control output of their own control signals using the switching cells 44 feed each other sequentially before switching on the control decoders 43 of the older M level, which carry out sequential control of the power supply to each individual multiplexer 48 entering into composition of block 7 multiplexers from

the first switch 8 to the inputs of the power supply 45-P th is formed at the output of the digital

neither unit 7 using the switching cells 45 of the first switch 8. Thus, at each separate time point of the UKEM operation, power is supplied only to one of the control decoders of each individual control level of control units 5 and 21 and only to one of the multiplexers and the decoders included in blocks 7 and 19, respectively, the search for a low level signal coming from the currently included decoder 49 on the data bus of block 19

Q 5 0 5 0 0

five

decoders, at all contact points of the Switching unit connected with the test object and thereby determining its connection, as well as the presence of a low-level signal on the test link connecting the output of this decoder to one of the information inputs of a specific multiplexer that is not directly connected to the object under test to monitor the operability of the device and to control the electrical installation regardless of the connections of the object under test.

The low level signal detected on any of the information inputs of any multiplexer 48 of the multiplexer block 7 is fed to the information output of block 7. Inverted into the level Bbicokoro signal, it is transformed to the first input of the first equivalence element 11, the first indicator 12 monitored communication, the first input of the communication number control unit 13, the information input of the mode setting unit 10 and performs the following functions: light indication of the presence of communication using elements 96 - 100 of the first state indicator 12 monitored communication; I changing the serial number of the monitored communication line on the falling edge using the second counter 77 of the address of the communication number control unit 13: transferring the digital matrix 15 of the memory from the storage mode to the information recording mode for the duration of its operation (valid only when The UKEM bot in the Recording mode specified in the 10 mode setting block) is opposed at the first input of the first element 11, which is equivalent to the signal at the second input of this element, which is

five

memory matrices 15 as follows. The address code of the end of the detected communication, formed at the address output of the first. on the address output of the first control unit 5, from the address output of the first block 9 of the verification program set, is compared on the equivalence element 52 with the end address code of the rare link formed by the outputs of the memory elements 50, sequential a number (address in the memory elements of block 15), which is determined by the next communication code formed with the first counter 76 at the address output of the switch 88 of the communication number control unit 13 and connected to the third address input of the block 15. Simultaneously The code of the start address of the detected communication formed by the address outputs of the second poll counter 20 and the control counters 42 of the second control block 21 connected to the address output of the second check program block 23 to the second address input of the digital matrix 15, is similarly compared. the address code of the beginning of the detected communication, formed by the outputs of the memory elements 51 of block 15 using the same next communication code as the end code of the detected communication. According to the results of comparing the above codes, the addresses of the beginning and end of the detected communication formed during the test with the codes formed by the memory elements 51 and 50, respectively, in block 15 of the digital memory matrix, the output of block 15 produces a high level signal only when absolutely unambiguous From block 15 output

the digital memory matrix, the signal of the high output of the third equal-level element 24 is transformed to the second (first input of the first equivalence element 11, the input of the second indicator of the controlled communication state 16, the second input of the communication number control unit 13 and performs the following functions: light induction of the presence of communication with the help of elements 96 - 100 of the second indicator 16 of the state of the controlled communication; changing the state of the first counter 76 of the control unit 13 of the number of communications that forms the next communication address code d elements, 50 and 51 of the memory of the digital matrix of the memory 15, opposes at the second input of the first element 11 equivalence to the signal at its first input from the output of the multiplexer block 7, the formation of which was described above. inputs of the equivalent element 11 at its output A low level signal is formed, which in turn generates a high level signal at the output of the second element 14 I, as a result of which the state changes with a clock pulse of a generator and 1

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value, which changes the address output of the second poll counter 22, which in turn changes the code of the next communication start address. The formation of signals in blocks 20, 21 and 23 is similar to the formation of signals in blocks 8, 5 and 9, respectively. The coincidence of the code values at the address outputs of the second polling counter 22 and the control counters 42 of the second control unit 21 with the code at the outputs of the trigger cells 66 and 67, respectively, of the second test program setting unit 23 generates a short high signal that sets the counters to zero. After the inversion on the element 38 of the unit 6 unit of the device, the high level of the signal at the control output 4 cuts off the power of all the decoders and multiplexes. moat UKEM. and the low level of the signal at the control output 1 prohibits the passage of clock pulses to the input of the first 4 polling counters, " The result of the test performed allows to judge the signal at the output

0

five

the first counter 4 of the fire and, as a result, the change of the states of the control meters 42, the decoders 43, the controls of the first control block 5, the information inputs of the multiplexers 48.1 - 48.K of the multiplexer block 7, as well as using elements 44.2 - 44.N and 45.1 - 45, To the first switch 8, a parallel-serial power connection to the decoders 43.2 - 43.N of the first control unit 5 and in series to the multiplexers 48.1 - 48.K to the multiplexer unit 7, respectively.

When the values of the codes formed at the outputs of the first poll 4 poll and the control counters 42 of the first control block 5 coincide with the code set at the output of the trigger cells 66 and 67 of the first block 9 of the verification program, elements 68 - 74 of the same block , a short high-level pulse is generated at the control output, which sets the first poll count 4 and the control counters 42 of the first control block 5 to the zero state, and a pulse is also generated on

five

0

five

0

five

A value that changes the address output of the second poll counter 22, which in turn changes the code of the next communication start address. The formation of signals in blocks 20, 21 and 23 is similar to the formation of signals in blocks 8, 5 and 9, respectively. The coincidence of the code values at the address outputs of the second polling counter 22 and the control counters 42 of the second control unit 21 with the code at the outputs of the trigger cells 66 and 67, respectively, of the second test program setting unit 23 generates a short high level signal setting the counters to zero. After the inversion on the element 38 of the unit 6, the device starts up, the high level of the signal at the control output 4 cuts off the power of all the decoders and multi plexors UKEM. and the low level of the signal at the control output 1 prohibits the passage of clock pulses to the input of the first 4 polling counters, " The result of the test allows to judge the signal at the output

17

the control of the communication number control unit 13, which controls the result control indicator 17 and is configured as follows. The number of connections, the quantitative value of which was determined above, set at the output of the trigger cell 80, is compared with the end of the second counter 77 of the number of connections detected in the test object and the first counter 76 of the number of connections containing the digital matrix 15 of the memory , but only those which by the code of the address of the beginning and end of the communication, as well as the serial number of the communication line coincided with those found in the test object, In the case of coincidence of signal levels at the matching inputs of elements 81 and 82 of equivalence, 87 and, in general, the communication number control unit 13 Normalizes the low-level signal, whose presence is indicated by elements 91-95 of the result control indicator 17, and allows judging the reliability of the test of the test object and the health of the device as a whole,

The second 3 and third 24 elements of the same network perform the function of the OR logical element and, in addition to the signaling described below, transmit signals for presetting the code of the address of the beginning and end of the tested communication at the request of the operator, i.e. random check of individual connections.

The case of correct execution of electrical installation in the test object of the full performance of the UKEM and the absence of faulty situations during the test according to a given program was considered.

Suppose a link is detected, whose presence in the subject

j object is not provided (extra connection). At the output of block 7 multiplexers and, accordingly, at the first input of the first equivalence element 11, a high level signal appears, but the same code of the address of the beginning and end of communication by the code of the address of the communication sequence number from block 13 controls the number of links in the element 50 and 51 of the digital matrix 15 of the memory is absent, as a result of which the high level of the signal at the second input of the first element is equivalent to

ten

f5

20

25

-JQ.

69884318

no form. Consequently, the high level of the output signal - the equivalence element 11 and the first input of the second element And 14 Generates at the output of the second element 14 And the third input of the first element 2 And a low signal level, which prohibits the passage of clock pulses from the generator 1 to the information input of the first counter 4 survey. At the same time, the luminescence of the first 12 and the absence of that of the second 16 indicators of the communication state indicate that the subject under test is ji44He, and the code of the address of the beginning and end of the detected communication is decrypted. , indicator-counters and in alphanumeric form are displayed on LED indicators (in FIG. 1, no communications are indicated; for the operator to register, the combination of high and low levels of signals at the inputs of the first 12 and second 16 indicators of the communication status are code for determine whether frost or inadequate communication in the test object.

The discovery during the test of the test object of a missing link is similar, but a high vposeHb signal is formed at the second input of the first equivalence element 11

After registering the character, the code of the address of the beginning and end of the error communication

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55

by the operator, to the second input of the third equivalence element 3 from the output of the control unit 6 of the device start-up, a short unit-level high signal enters, changing the state of the code of the output output of the first counter 4 polling per unit younger, upwards, thereby the address code of the end of the detected erroneous communication is changed and the test of the test object continues. .3 unit 6 start the device The formation of the specified signal at the control output is carried out by a single pressing of the Set control button 36, 2 and subsequent one-time pressing of the control button 35 Ј2. after registration of any detected, erroneous connection.

The performance monitoring of the UKEM is realized through the Cto-Sco connections specifically defined for this purpose, which are included in the data bus of the block 19 of decoders, which are directly connected to the specific information inputs of the corresponding multiplexers of block 7. In the proposed device, these links correspond to the output of the decoders of the block 19 and the corresponding multiplexers of the block 7 with the zero value of the code on the address outputs of the second 22 and first 4 polling counters, i.e. at the moments of time defining the inclusion of one or another decoder or multiplexer into operation from the second 20 and first 8 switches. The absence of any of these connections, or their combination in any other combinations with the connections of the test object, determines the malfunction of the MCEM, and the address of the beginning or end of the communication easily determines the faulty element.

The control of the number of connections by comparing the values of the codes of the number of connections detected during the test of the test object, the first counter, controls the presence or absence of faulty situations of any kind that are possible when testing a test object or writing information to a digital memory matrix 15. 77 and the number of connections corresponding to this test object, the second counter 76 with a trigger cell code value 80 of a priori known number of connections corresponding to this test object. The glow of the result control indicator 17 is carried out if, and only when, all the connections of the test object correspond to the circuit design embedded in it, all the elements of the device are operational and there were no failures in the ECEM operation during the test.

The recording mode of a priori known information in the memory elements 50 and 51 of the digital matrix block 15 of the UKEM memory is performed similarly to the verification mode, but you must first set the Record mode by pressing the control button 56 of the mode setting unit 10. At the same time, the outputs of the control unit 10 are set to signals whose levels correspond to the information storage mode in the memory elements 50 and 51 of the unit 15. The presence of a high level signal at the information input of the unit 10 from the multiplexer unit 7 to

0

five

0

five

0

five

0

45

50

55

the duration of this signal translates the memory elements 50 and 51 of block 15 into the mode of recording the start and end address code corresponding to the test communication object, while the address number of the communication number generated by the first counter is present at the address inputs of the memory elements. 77 At the output of the second switch 89 of the block 13 controlling the number of connections With the inclusion of the UKEM in the Record mode, a low level signal appears at the information output of the block 10, which by its presence at the second input of the second element I 14 provides the conduct mode stop. Checking the correctness of the recording of information is carried out by luminescence of the result control indicator 17, as well as the transfer of UKEM to the Control mode, when the source of information about the test object becomes the test object. The test unit for testing commercially available products can use separate blocks as memory elements of block 15. EPROM, RPZU or floppy disks corresponding to a specific type of product being tested.

In the proposed EEM, RAM, used as memory elements of unit 15, is provided with combined power from external sources and built-in portable batteries for long-term storage of information, as well as manipulation with any of the control buttons included in the EEM, are accompanied by LED indication ( items not listed).

Claims (1)

Invention Formula A device for controlling electrical installation, containing a switching unit of the test object, the first and second indicators of the state of the monitored communication, the first equivalence element, the multiplexer unit, the decoder unit, the first and second interrogation counters, a clock generator whose input is connected to the first input The first element And, the second input of which is connected to the first control output of the device launch unit, characterized in that, in order to expand the functionality, reliability and efficiency of control, the second and third elements of equivalence are entered into it, the first and second control blocks, the first and second switches, the first and second blocks of the assignment of checking programs, the set of modes, the digital memory matrix, the second element I, the control unit of the number a control unit and a result control indicator, the input of which is connected to the Control output of the block of the number of connections, the first input of which is connected in parallel with the first input of the first element of equivalence, the input of the first state indicator of the controlled connection, information input of the mode setting unit and information output of the multiplexer unit, the second input is connected in parallel to the input of the second indicator of the state of the controlled connection, the second input of the first equivalence element and the output of the digital memory matrix, the third input is connected in parallel with the second input of the second element And and information output of the mode setting unit, and the address output bus is connected in parallel to the third address input of the digital memory array, the first address input of which is parallel Connected to the address output bus of the first test program setting unit, the second address input is connected in parallel to the address output bus of the second test program setting unit, and the first and second control inputs are connected to the first and second control unit settings control outputs, the first input of the second element And connected to the output of the first element of equivalence, and the output is connected to the third input of the first element And, the output of which is connected to the first input of the second element of equivalence, the second input of which It is connected to the second control output of the device startup unit, and the output is connected to the information input of the first interrogation counter, the control input of which is connected in parallel with the first control input of the first control unit, the first input of the third equivalence element and the control output of the first test program setting block parallel 0 five 0 five 0 five 0 five 0 connected to the address input of the multiplexer unit and the first address input of the first test program setting block, and the information output connected to the second control input of the first control unit whose address output bus is connected in parallel to the second address input of the first program setting block, the enable input is connected in parallel with the enable input the second control unit and the turn-on output of the first switch, the input / output of which is connected to the fourth control output 1 of the device launch unit, the input control is connected in parallel to the control output of the first control unit, the first power output bus is connected in parallel to the power input of the first control unit, and the second power output is connected in parallel to the power input of the multiplexer unit whose information input, the input of the switching unit and the data output of the remote control unit & Rarators are connected by a data bus of the de-flator unit, whose address input is connected in parallel with the address output bus of the second interrogation counter and the first address input of the second block setting verification programs, the second address input1 of which is connected in parallel to the address output bus of the second control unit, the control output bus of which is connected in parallel to the control input of the second switch, the second output power bus of which is connected in parallel to the power input of the decoder unit, and the first power output bus in parallel connected to the power input of the second control unit, the second control input of which is connected to the control output of the second poll counter, the information input of which the third input of the third equivalence element, the second input of which is connected to the third control output of the device startup unit, the input of which is connected in parallel with the control input of the second interrogation counter, the first control input of the second control unit and the control output of the second program setting block - test. 25 8x. from 5l. 23 sx.ynP.2tFig. 2 from bl. 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