SU1688263A1 - Electrical wiring tester - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to control wiring in the manufacturing and manufacturing process. The purpose of the invention is to increase the speed of the device. The wiring control device comprises a checkpoint selection switch, a polling switch, an address decoder, a checkpoint register, a memory unit, a memory data register, a control unit, a display and manual control unit, a permanent memory address register and a permanent unit memory New in the device is the introduction of the data register of the RAM, the register of the address of the permanent memory, the RAM block and the block of the permanent memory. 16 il.

Description

The invention relates to automation and computer technology and may be used to control electrical installation in production and its manufacturing process.

The purpose of the invention is to increase the speed of the device.

Figure 1 shows the block diagram of the device, figure 2 is a functional diagram of the switch of the selection of the control point, on Lig.Z - the same as the switch of the survey; figure 4 - the same address decoder; 5 is the same as the checkpoint register; FIG. 6 is the same; the RAM block of FIG. 7 is the same, the RAM data register; Figure 8 is the same as the control unit; Fig. 9 is the same, the display and manual control unit; Fig. 10 is the same, the permanent memory address register; 11 is the same as a permanent memory block; on Fig - block diagram of the data preparation algorithm; FIG. 13 is the same, the algorithm of the monitored installation, in FIG. 14 the same, the algorithm of the program for controlling the finished installation; in fig. 15- data format for addressing contact numbers and corresponding slot numbers for recording them from the output of the main memory data register; in Lig.16, the data format for the contact connections and the number of circuits v arriving at the address input of the main memory unit for selecting contact addresses and corresponding slot numbers from it.

The device (AIG.1) contains the Switchpoint 1 selection switch, the I switch 2 polling, the decoder 3 ADO

00 00

Yu

oe with

peca, checkpoint register 4, random access memory (RAM) bpock 5, random access memory register 6, control unit 7, manual control indication unit 8, fixed memory address register 9, permanent memory unit 10 (ROM ), tires 11-36 connections between the device.

The switch 1 of the selection of the control point (FIG. 2) contains the keys 3 /, the number of which is determined by the number of contacts of one connector, the decoder 38 of the address of the connector and the trigger 39 for issuing information from the output of the switch 1.

The polling switch 2 (FG.C) contains the decoder 40 contact numbers, the number of which is determined by the number of contacts of one connector, the decoder 41 select a group of contacts, the decoder 42 connector numbers, the elements OR NOT 43, 44 and 45.

The decoder 3 addresses (.4) contains the decoder 46 select contact groups and 47 decoder contact numbers.

Checkpoint register 4 (FIG. 5) contains registers 48 for recording contact addresses.

The RAM unit 5 (FIG. 6) consists of memory elements 49 where the addresses of all the contacts of all the control circuits of the object are stored.

Register 6 (Lig.7) contains registers 50, which are single-chip microchips for entering and outputting information, for example,

380VB55.

I

Control unit 7 (Fig. 8) contains control unit 51 and register 52 for input and output of information. As the node 51, a single chip can be used for a microscopic computer from the K1816 series (for example, a BIS of the K1816BE35 type), I as a register 52 - the BIS of the KR580 type BB55A.

The display and manual control unit 8 (Fig. 9) contains a permanent memory (ROM) 53, which stores the codes of all characters and numbers used to display information on the screen of the information display unit 54, element 11PI-HE 55, multiplexer 56, intended to inform the control unit 7 about pressing one of the buttons of the keyboard 57, the counter 58 for addressing the multiplexer 56 and the element OR-NOT 59 for resetting the meter 58.

five

0

Register 9 (Fig. 10) contains a register 60 for recording address codes for block 10 (Fig. 11), consisting of an element of the ROM 61, which stores the programs of the device for checking wiring in the data preparation, checking the completed and finished installation. , the algorithms of which are shown respectively on Fig-14.

The device works as follows.

The device can operate in the following modes: data preparation, check of the finished installation, and control of the performed installation.

The essence of the device in the data preparation mode is as follows. On the keyboard 57, controlled circuits are typed in the form

five

0

five

five

0

five

X And, - ,.

XN; p,

...,,

where x n

n i

1 i

connector designation is the serial number of the connector of the monitored object; number of the contact being checked; the sequence number of the contact address of one monitored circuit,

the key to close the controlled circuit, for example, XB.ZA, X10.4B, X5.3B, X2.3A, X12.5, which means that the contacts X1.3A, X5.3B belong to the 1st controlled circuit, and X2.3A, X12.5 - 2nd controlled circuit. So, if node 8 of displaying information of block 8 has 16 familiarity, then to transfer a line, press the Transfer key of the keyboard 57 key and continue to type addresses of the contacts of the monitored circuit.

The operation of the device in the mode of data preparation on the example of input into the device of the second controlled circuit X2.3A, X12.5.

The device is reset to the initial state by the signal Reset on the bus 15 from the block 8. This signal clears the registers 50 of the block 6 intended for storing the addresses and data received from the block 5 and the block 7 of the control. When receiving a control signal about programming the RAM through bus 17 from the control panel of unit 8 (for this you need a toggle switch, use keyboard function 57 of block 8 to set to Data preparation) node

51 refers to the tone of the part of the program recorded in the element of the ROM 61 of unit 10, from where the execution of the data preparation program begins. Node 51 is written over bus 32 to register 52 of block 7, a four-bit address of familiarity (0000), which is bus 30 of register

52 enters the input of the node 54 of the block 8. The next clock of the block 7 via bus 20 generates an address strobe and starts programmatically generating rectangular pulses with a frequency of 3 kHz via bus 21 to the input of the counter 58 of block 8, the output of which is connected to the address input of multiplexer 56 and through the OR element -Not - to the input of the initial installation.

When you press the keys X on the keyboard 57 of the block 8, a pulse gate appears at the output of the multiplexer 56, which via bus 16 enters the input of node 51 of block 7, after which it generates the bus 32 of the binary address of the cell 53 of block 8, where all key codes of the keyboard 57 for displaying them in node 54. This address is written by the control signal via bus 28 to register 60 of block 9 and via bus 31 to the input of the ROM 53 of block 8, from the output of which the binary code of the corresponding key is fed to the information input of node 54 . The next beat block 7 on the bus 19 g wind farms gating information which is recorded a binary code of the pressed key in node 54 and displayed on the screen.

After this, a counting counter of the number of monitored circuits (in this case 00000000) is installed and its binary code is written to bus register 33 via bus 32, register 50 of register 6, from which output it goes to bus address 34 on bus 34 49 of block 5. The next clock program sets the count of the number of addresses of the monitored contacts of one circuit (0000 in this case), and its binary code is also written by bus signals 33, 23, 25 via bus 32 to register 50, from which output bus 34, it arrives at the address inputs of memory elements 49 of block 5.

After that, node 51 of block 7 polls the bus 16 software conditionally. After pressing the key 2 of the keyboard 57 of block 8, the write cycle is repeated

five

0

five

0

0

0

the binary code of the character to the information display unit 54, it is initiated on the screen and programmatically stored in the internal RAM of the processor of the node 51. The next cycle of the node 51 of the block 7 programmatically polls the bus 16 again. After pressing the keys of the keyboard 57 of the block 8, the binary the sign code to node 54 and the next clock cycle, the binary code of the slot number (2) of the control signals via buses 33, 25, 23 is written over bus 32 to register 50, from the output of which bus 34 goes to the input of the data of memory elements 49 of block 5. Thus way n the processor of node 51 of block 7, programmatically deciphering the binary code of the character., writes in register 50 of register 6 the binary code of the slot number entered previously from the keyboard 57 of block 8.

With the next clock cycle, node 51 of block 7 again polls software state 5 of bus 16. After pressing keys 3, then A of keyboard 57 of block 8, the cycle of writing binary codes is repeated. 3 and A to node 54, and these characters are initiated on the screen. After pressing the keypad, the keypad 57 displays the binary code of the sign of the control signals on the control buses 33, 25, 23 in the register 50, the output of which via the bus 34 is fed to the inputs of the data of the memory elements 49 of the block 5. 5 The buses 26 and 27 from the output of the register 52 of the control unit 7 are written to the binary address of the first contact of the first monitored circuit in the memory 49 of the unit 5.

By the next clock, the count counter of the number of addresses of the monitored contacts is programmatically incremented by one and its binary code by bus signals 33, 25, 23 is written over bus 32 into register 50, from which output bus 34 arrives at address inputs of memory elements 49 of block 5.

Thereafter, the node 51 of the block 7 again polls the bus 16 software conditionally. After pressing the x, 12,., 5 keys, respectively, is repeated. an algorithm for writing their binary codes to node 54 and data to the memory elements 49 described above.

Pressing the key indicates the end of the recording of one monitored circuit.

five

0

five

Node 51 of block 7 programmatically increments the count of the number of addresses of monitored contacts by one, the control signals on buses 33, 25, 23 write its binary code to register 30 on buses 32, from the output of which it goes to the address inputs of Memory 49 bus 34, then bus 32 also controls the bus signals 33, 25, 23 to write the binary code 111111111111 to the register 50, from the output of which it goes to the data input of memory elements 49 and the bus control signals 26 and 27 is written to RAM. In the next cycle, the counter of the number of monitored circuits is incremented by one, the count counter of the number of contacts of one monitored circuit is zeroed and the cycle of writing their binary codes into the register 50 repeats, from which they get to the 34 49. In a similar way, other controlled chains are introduced.

After entering into the device all the monitored circuits, it is necessary to switch the switch of the keypad 57 of the unit 8 to the VM Control or GM Control position.

The device can be used instead of the memory elements 49 of the ROM, where the addresses of all the contacts of the monitored circuits will be stored, which greatly increases the reliability of the device (eliminating operator errors when entering data into the device). The simplicity of entering data on monitored circuits, the ability to use data ROMs, and the autonomy of the device (without a control computer) of data increase the efficiency of the device compared to its counterpart.

The operation of the device for the control of electrical installation in the test mode of the finished installation (GM).

Set the switch of the operation of the keyboard 57 of the block 8 to the position Control GM. When the start button of the keyboard 57 is pressed, the node 51 of the block 7 calls to that part of the program where the monitoring program of the GM starts, and with the first clock cycle the count of the number of monitored circuits and the number of addresses of the contacts of one monitored circuit wrap. Next tact node

five

0

0

five

five

51 generates their binary codes via bus 12 and with control signals via buses 33, 25, 23 writes them into register 50, from which they go through bus 34 to address inputs of memory elements 40 of block 5. Next time with control signals via bus 26 and 27, from the output of the register 52 of the control block 7, data is read from block 5, from the output of which, via bus 12, they are fed to the information input of the register 50 and the address inputs of the address decoder 3, the polling switch 2 and the control point selection switch 1. From the output of address decoder 3, the decoded address of the first contact of the first monitored circuit is fed to the input of register 4 of the control point and with the next clock control signal via bus 14 from the output of register 52 of block 7 is written to register 48 and trigger 39 is activated, from which a high level allows the signal to flow a positive level to one of the inputs of the object to be monitored, and control signals through the buses 22, 24 via the bus 32, the binary code of the contact address is fed to the input of the node 51 of the block 7 and is stored.

With the next clock, the counter of the number of contact addresses of the first monitored circuit is programmatically incremented by one and its binary address is recorded in the register 50. Control signals for buses 26 and 27 are read from block 5 the second contact address of the first monitored circuit and for bus 12 are fed to the information input of register 6 and address inputs of the address decoder 3, polling switch 2 and checkpoint selection switch 1. The next cycle of control signals via buses 22, 24 is the binary code from register 50 to buses 32 arriving at the input of processor node 51 and being software analyzed for equality to its units (111111111111), which indicates that the verification of all addresses of the monitored circuit is completed. If the binary code consists of all units, the counter of the number of monitored circuits is programmatically incremented, the counter of the number of addresses of the monitored circuit is zeroed and their binary codes are written into the register 50 g iI

If the binary code is not one, it is decrypted by switch 2.

polling and the next clock, node 51 polls the state of bus 13. When there is a high level, which means establishing a connection between the first and second contact addresses of the first circuit, the counter of the number of addresses of the circuit under control is programmed and the test cycle repeats.

If there is a low level on bus 13, which means lack of communication, node 51 of control unit 7 performs a write cycle (described above) to node 54 of contact address addresses about the absence of communication between them, for example X2, FOR XI0 34 (sign means no link zi).

In the next cycle, the node processor 51 polls the state of the control bus 17 and, if there is a high level (when the Continue button is pressed, the keypad 57 of block 8) continues to work.

The first address of the first monitored circuit is permanently stored in register 4 of the control point. When analyzing the next monitored circuit, the counter of the number of addresses of the monitored circuit is nullified, the counter of the number of monitored circuits is incremented by one and their binary codes are generated by the processor over bus 32 and control signals for buses 33, 25, 23 are recorded in -register 50. The next clock signals control via buses 26 and 27 reads the binary code of the 1st address of the monitored circuit, which is followed by control signals via tires 22 and 24 to the input of node 51 of block 7 via bus 32 and stored in the internal OZ node 51. The next clock cycle node 51 interrogates the state of the tire 13 and with the high level outputs of the block assembly 54 8 information about the presence of excess bond, e.g. 32J3A H1.15. The mark indicates the presence of an extra link.

When you press the Continue button on the keyboard 57 of block 8, the device continues to work in GM mode. i

If there is a low level on bus 13 (which means no communication), the counter of the number of monitored circuits is incremented by one, the counter of the number of contact addresses of the monitored circuit is reset, and their binary codes are written to register 50, selected from block 5

.

ten

15

20

25 5 0 5

0

thirty

. the first address of the monitored circuit and the test cycle is repeated.

Thus, in the GM check mode, there is no need to search all contact addresses of the monitored object to identify an extra link or no link, but it is enough to check whether there is a link between the contacts in one monitored circuit and no link of the first contact addresses of each monitored circuit. among themselves, which increases the speed of the device several times.

The difference in device operation in the mode of installation (VM) is that the operator dials one monitored circuit at block 8, switches the Keyboard operation 57 switch to VM mode and, after pressing the Start button on the keyboard 57, the device executes the VM control program.

Register 4 of the control point records the first address of the monitored circuit and first enumerates the next (in order) contact addresses of the monitored circuit for the presence of a link, and then all the addresses of all other monitored circuits for the presence of an extra link.

In the control mode of the VM, it is advisable to use in the device instead of the memory elements 49 of the RAM block 5, where the addresses of the controlled circuits stored in them are stored in advance, which increases the reliability of the device.

Claims (1)

Invention Formula A device for controlling electrical installation, containing a checkpoint register, an address decoder, a polling switch, a group of information inputs of which are connected to a group of outputs of a switch of selecting a control point and a group of inputs and outputs of a device, a control unit connected to the first output and the first synchronizing input of the control register points and exit switch polling, and the display unit and manual control, the first and second outputs of which are connected respectively to the inputs reset Sa and the second synchronization input of the control unit, characterized in that, in order to increase the speed of the device, a RAM block, a fixed memory block, a RAM data register and a permanent memory address register are entered into it, the first group the outputs of the control unit are connected to the group of control inputs of the RAM data register, the output group of which is connected to the information group of inputs of the RAM unit, the output group of which is connected to the groups of address inputs mmutator polling ,, register data-. The main memory, the input address decoder input group, and the first address input selection switch group, the second address input group of which is connected to the output register group of the control point connected to the information decoder output group, the address select switch control input point is connected to the first output of the control unit, the group of input-output of which is connected to the groups of information five 0 of the main memory data register, the constant memory address register and the group of outputs of the constant memory block, the synchronizing input and the group of address inputs connected respectively to the second output of the control unit and the group of outputs of the register of the constant memory whose synchronizing input is connected with the third output of the control unit, and the output with the enabling input of the data memory register and the input of the condition of the control unit, the second and third groups of outputs of which are connected respectively to groups of control inputs of the main memory unit and the display and manual control unit, a group of outputs and the first and second groups of address inputs of which are connected respectively to the group of address inputs, the fourth group of outputs of the control unit and the output group of the address register of the permanent memory, and the first output - with the reset input of the RAM data register. 1 mf 9Z C928891 // tt-t tt --- ttt -.- t 37 31 cjL acj2L 35 a 38 - 39 Schi 2. 12. H W W ill Lk t 4Z teJ 37 ЈG eleven 40 40 s fl / g la i  h "  -with § } o- os os mr o- and;  | 1 §5 %  one, gf 8 II (Tfyva / to j ffaffart efjftc. k-ai constantly if UCflV DttCft / nt / plb HO MSNNN1 ef) cheap eftjrt g-biif njpfc. K di C7M Dtictfmum on HtooyoD / ffuiyre uA3.t j X-s / ± lL WwupPifcimb t-t / u "Spec, t-oa chains J X-, 2, -, d $ -N., N (n / 0 / t fo tflenewf K-QV l / ffll / J totJS l - / 1 .. t fiftl - total number-fo targets) y, - fris (O. YL-lo connections tefaiu qfnv) Yu n-col-So compound / faMou yf / n / Horn. /four // 19 s SPTA Mi / pi tgiivt cat ta t controls ofmms (--r} FIG. is / d | / g | t | / 7 thrash / C0Jt // 0fo # / t afyecq / r -M is intact Phage. f6 "N l l KofapofQHV HO coefnqfMbfx pen VCFCfQftf KQHmpOJ (/ pyt pogo ofotKmq