US3603986A

US3603986A - Events recorder

Info

Publication number: US3603986A
Application number: US794657*A
Authority: US
Inventors: Ben A Harris
Original assignee: Rochester Instrument Systems Inc
Current assignee: Rochester Instrument Systems Inc
Priority date: 1969-01-28
Filing date: 1969-01-28
Publication date: 1971-09-07
Anticipated expiration: 1988-09-07

Abstract

A sequential operations events recorder is disclosed wherein alarm points or circuits are monitored for providing a printed record in alphanumeric characters the changes in state or event of each of the alarm points or circuits in timed sequence. The first of a series of events is documented in printed form by the recorder to feature a ''''first out'''' indication.

Description

United States Patent Ben A. Harris lrondequoit, N.Y.

Jan. 28, 1969 Sept. 7, 1971 Rochester Instrument Systems, Inc.

{72] Inventor [21 1 Appl. No. [22] Filed [45 I Patented [7 3 Assignee [54] EVENTS RECORDER 8 Claims, 5 Drawing Figs.

[52] US. 340/415, 340/412, 340/213, 340/324 [511 m. (I osh 19/99, H04q 3100 50 Field oISeareh 340/213,

INVERTER NETWORK CIRCUIT osrecron "'l cmcurr DETECTOR L. cmcurr M3355 cmcun' 20 V (RESET) [56] References Cited UNITED STATES PATENTS 2,963,692 12/ 1960 Barter et al. 340/251 3,029,421 4/1962 Beguin 340/415 3,138,791 6/1964 Beguin 340/415 3,264,613 8/1966 Stolle 340/223 3,264,626 8/1966 Mounce 340/2131 Primary Examiner-John W. Caldwell Assistant Examiner-Robert J. Mooney Attorney-Samuel R. Genca ABSTRACT: A sequential operations events recorder is disclosed wherein alarm points or circuits are monitored for providing a printed record in alphanumeric characters the changes in state or event of each of the alarm points or circuits in timed sequence. The first of a series of events is documented in printed form by the recorder to feature a first out indication.

SELECT GATE MEMORY CIRCUIT ABNORMAL PATENIEU SEP 1 I97! SHEET 2 BF 3 Na om M535 omoumm mum vm J zmozmd m. w CD050 mohowkmo now INVENTOR. BEN A. HARRIS Fl'go N 6d+ on 1 63+ ATTORNEY SHEET 3 [IF 3 -(HI)VOLTS +(L0) VOLTS 6 L IL -(LO)VOLTS 38 Fig. 3

PATENTED SEP 7 mm m m E V m BEN A. HARRIS BELL RET

STA

PAU

PAT

. to normal and a permanent record of a time sequence of the variable and its identification is recorded.

BACKGROUND OF THE INVENTION Prior art annunciators employing illuminated displays are well known to those skilled in the art. Such annunicators have been used in thepast for displaying by illuminated panels'the change in state viz normal or abnormal of many alarm points or circuits in a system. A change in state in one of the alarm points in the past usually required a manual correction in the system before the system returned to the normal state. With the advent of automatic equipment many of the alarm points are self-correcting so that the illuminated panels in the annuneiator may only momentarily display a fault or change in state of the alarmpoint. Thus this information is very volatile since no record of the change of state or event is produced. Furthermore it is particularly important to know when the first-alarm point goes abnormal in such systems. While prior art annunciators have worked satisfactorily in the past, they have not been entirely satisfactory for automatic self-correcting systems since no permanent record of the change of events is recorded. Accordingly, there is a pressing need for a recording annunciator which will record the events of each alarm point or circuit in a system in code form such as alphanumeric characters and also give a first out" indication.

I SUMMARY OF THE INVENTION Briefly described, an events recorder in accordance with a preferred embodiment of the invention comprises a plurality of monitor circuits each of which is coupled to a corresponding alarm point orv alarm circuit. The monitor circuits in response to an interrogative signal produce a first signal indicating a change in status (normal to abnormal or abnormal to normal) of the alarm circuit and a second signal indicating the status. Scanning means sequentially provide the interrogation signals to the monitor signals when enabled. A display means functional circuit also provides a series of sequential control signals when enabled. Switching means are coupled to the monitor circuits, scanning means and display means functional circuit for disabling the scanning means to continuously interrogate the monitor circuit producing the first signal and enable the display means functional circuit. A signal responsive output display means or device such as a signal responsive automatic typewriter, Teletypewriter or the like is included. A circuit means-is coupled to the output display means, scanning means, the plurality ofmonitor circuits and the display means functional circuit. The circuit means is responsive to the control signals to apply signals to the output display means identifying the monitor circuit being continuously interrogated, and indicating its status. A reset circuit means is coupled to the monitor circuits for removing the first signal in the monitor circuit being interrogated to disable the display means functional circuit and enable the scanning means when the status indication is completed on the display means. The monitor circuits are sequentially monitored so that the first monitor circuit and its associated alarm circuit which changes status is so indicated on the display means.

, BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is ablock diagram of an events recorder showing apreferredembodiment of the invention;

FIG. 2 is a schematic diagram of the input modules included in the events recorder-of FIG. 1;-

FIG. 3 is a schematic diagram of detection circuits included in the input module of FIG. 2;

FIG. 4 is a simplified schematic diagram of portions of inverter-network and memory circuits included in the input module of FIG. 2; and

FIG. 5 illustrates an example of the timing sequence for transferring information to the output display means included in the events recorder of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT The events recorder of the present invention provides for a visual and permanent indication of the type of change in status of alarm-circuits, the location or identification thereof, and time and sequence of occurrence, in a coded or alphanumeric form, thereby providing sufficient information so that immediate steps can be taken to provide proper maintenance. The change or event to occur first is recorded first, followed by subsequently changing alarms in a time of occurrence sequence, or interrogation sequence, depending upon the rate at which the changes occur. The events recorder also includes interrogation means for providing a summary of events for all of the alarm points in which a change occurred.

The events recorder illustrated by the basic block diagram of FIG. 1 continuously scans a large number of alarm circuits or alarm contact points 20a20n to detect any change in their status (on to off, open to closed, etc.). When a change in status of an alarm point 20a-20n is detected, the scanning stops and the identification of the alarm point 20a-20n, type of change (normal to abnormal or vice versa) and the time the change of status occurred, is then recorded by an output display device 10. The output display means or device 10 can be a printer, teleprinter, automatic signal responsive typewriter and the like, that prints a hard copy or permanent record in an alphanumeric form. Although the events recorder of FIG. 1 is described as monitoring relay contacts 20a-20n and recording their status on the output display device 10, it will be apparent from this description that the present invention is equally applicable to monitor other types of alarm points, contacts, transducers and the like, to provide a display on a variety of output display devices without loss of advantage, or the necessity of material change or alteration beyond that obvious to one skilled in the art.

The same reference numerals have been used through the figures in the drawings to designate the corresponding elements wherever possible so as to maintain closer correspondence between the respective figures thereby facilitating a ready understanding of the relationship therebetween.

Referring now to FIG. 2, the events recorder includes an inputmodule 11 that continuously monitors the status of the alarm circuits or field contacts 20a20n, where a represents the first contact and n represents the n" contact of a plurality of contacts 20a-20n. The. input module 11 includes a plurality of monitor circuits 20-211 corresponding to the contacts 20an, that is a separate monitor circuit 2a-2n is employed for each of the field contacts 20a-20n. The monitor-circuits 2a-2n detect, remember and indicate any change in the status of its connected alarm circuits or contacts 20a20n, respectively.

Each of the monitor circuits 2a-2n is identical. Each monitor circuit 2a-2n includes a correspondingly lettered detector circuit (l2a-l2n), an inverter-network circuit (Ma-Mn), memory circuit (l6a-16n) and a select gate circuit (I8a-l8n In the preferred embodiment illustrated, the alarm circuit or contacts 20a-20n include normally open contacts indicating a normal operating condition, however normally closed contacts or other types of switching devices such as transducers can also be used to provide an indicating variable, such as a presence or absence of a signal.

' It should be understood that the field contacts or contact points 20a-20n are representative of normal or abnormal conditions and may for example be included in alarm contacts or transducers that are conventionally connected to a system or apparatus to be monitored, such as turbines, generating stations, unmanned substations, etc. The contact points 20a20n and associated relays (not shown) are energized or deenergized when the monitored temperature, pressure, voltage, etc., reach an overload or abnormal condition to produce an alarm signal.

A separate schematic diagram representative of the detector circuits l2a-l2n is illustrated in FIG. 3. Each of the detector circuits l2a-12n comprises a relay which includes a coil 24 and corresponding contacts 38 that are activated in response to a change in status of the connected one of the alarm contacts (a-20a). The detector relay coil 24 is connected in series with a diode 26 and a resistor 28 between a negative low voltage (about 24 volts) at a terminal 30 and a negative high voltage (about 100 volts) at a terminal 32. A diode 34 is connected across the coil 24 to prevent high voltage spikes when the coil 24 is deenergized. The alarm contacts 20a (in the case of detector circuit 120) are connected between a positive low voltage (about 24 volts) at a terminal 36 and the junction of the diode 26 and the resistor 28. When the contacts 20a are open the diode 26 is back-biased and the relay coil 24 is deenergized. When the contacts 20a close, the diode 26 is forward biased and the relay coil 24 is energized to close its contacts 38. The relay coil 24 remains energized as long as the connected alarm contacts 20a remain closed.

When the alarm contacts 20a-20a initially close, the high voltage across the contacts (about 124 volts) provides an arcing effect that cleans the contacts and assures a low impedance connection for current flow between the terminals 36 and 32 (FIG. 2). This is important since the alarm contacts 20a-20 are often located in areas subject to adverse ambient conditions, such as high humidity and variable temperatures which may produce excessive corrosion. Corroded alarm contacts tend to present poor electrical connections that often severely limit current flow and reduce their reliability. The arcing effect of the high voltage across the contacts 20a-20n eliminates or substantially minimizes this detrimental effect of corrosion.

The detector relay contacts 38, when closed, connect the common line 40, or ground, to an inverter circuit 42, a resistor 44 and a terminal at 50 designated as NC (normally closed) and NO (normally open) (FIG. 2). The output of the inverter circuit 42 is connected to NO terminal, a resistor 46 and a capacitor 48. A connection is made between the NC terminal or the NO terminal and an output terminal 50 depending upon the type of contact point 20a employed. In the embodiment illustrated, the contact points 20a-20n are normally open (NO) and are in the open condition during normal operation and the connection made between terminal 50 and the NO terminal. If the contact points 20a were a normally closed (NC) contact point then the connection would be made between the NC terminal and terminal 50. Thus the connection made between terminal 50 and the NC terminal or the NO terminal is a permanent connection and does not change once set. The resistors 44 and 46 are connected to a positive low voltage power supply (about 5 volts) at a terminal 52. The opposite end of the capacitor 48 is connected to an output terminal 54.

The memory circuit l6al6n includes a pair of NOR

gate circuits

60 and 62 connected to form a latch type of flip-flop circuit (60,62) (FIGS. 2-4). The particular logic circuits illustrated in FIGS. 24 employs negative logic," that is a high level voltage represents a logic 0 whereas a low level voltage represents a logic 1. It should be understood of course that other logic schemes may be used without departing from the invention. The latch flip'flop circuit (60,62) employs a normally undesirable contact resonance or bounce (characteristic to most electromechanical switches) to an advantage by using the resultant pulsating signals to latch" the flip-flop circuit (60,62). When the detector relay coil 24 is energized, the contacts 38 are rapidly brought together. However, due to the resiliency of the contacts 38, the contacts 38 bounce apart several times before they come to rest and are securely connected. It is well known to those skilled in the art that uncom pensated contacts do bounce" and are generally cheaper than compensated contacts such as mercury wetted contacts. Thus less expensive contacts may be used in the practice of the present invention even though they are normally undesirable because of contact bounce.

The bouncing of the contacts 38 causes a varying direct current voltage or pulsating signal on the output of the inverter circuit 42 which charges the capacitor 48 through a resistor 64 and the series diodes 66-69 which define a reactive circuit.

When the capacitor 48 becomes sufficiently charged at output terminal 54 to produce a logic 0 at the input circuit 70 of the NOR gate 60, the flip-flop circuit (60,62) is latched to produce a logic 0 at its output terminal 61. When the relay is deenergized, a single pulse is produced appropriately polarized for latching the flip-flop circuit (60,62). The flipflop circuit (60,62) could also be latched by applying a logic 0 to a second input circuit 72 of the NOR gate 60. The flip-flop circuit (60,62) is unlatched by applying a logic 0 to the input 74 of the NOR gate 62. The flip-flop circuit (60,62) is latched whenever there has been a change in the status of the connected alarm contacts 20a from a normal" open condition to a closed abnormal" or alarm" condition, and vice versa (provided the flip-flop circuit (60,62) has been previously unlatched").

The memory circuits 16a-l6n also include a pair of NOR gate and 82 (FIG. 2) connected to enable the

input circuits

72 and 74 of the NOR gates 60 and 62 (flip-flop circuit) respectively. The NOR gate 80 is enabled to latch" the flipflop circuit (60,62) when the events recorder is in a summary mode of operation that is when the summary push button circuit 120 is operated. The NOR gate 82 is used to unlatch" the flip-flop circuit (60,62) during a recording mode of operation. The operation and function of the NOR gates 80 and 82 will be fully explained hereinafter.

The select gate circuits l8a-l8n each include a NAND gate 86 and two NOR gates 84,85 and are periodically interrogated in consecutive order by a scanner decoder circuit 88 (FIG. 1 One input circuit of each of the NAND gates 86 in the select gates l8a-l8n is connected to a separate terminal (designated XI, X2Xn) while the other input circuit is connected to a common enable terminal 7 (FIG. 2). The terminals X1, X2-Xn and 7 are connected to sequentially receive enable pulses from the scanner decoder circuit 88 to sequentially enable the select gate circuits l8a-l8n for interrogation in consecutive order.

When the NAND gate 86 is enabled, a logic 0 is applied to' one input circuit of the NOR gates 84 and 85. The NOR gate 84 is enabled only if it receives a logic 0 from the NOR gate 60 (the flip-flop circuit is latched") indicating a change in the status of the alarm contacts 20a. When enabled, the NOR gate 84 produces a record" signal on an output terminal 90 through a diode 92 for initiating a recording mode of operation. The second input circuit of the NOR gate is connected to the terminal 50 and receives a logic 0 when the alarm-contact 20a is in the abnormal condition to develop a logic 0 at the signal terminal 94 through a diode 96. Hence, if the alarm contacts 20a changed from a normal to an abnormal condition (open to closed) a record" signal (logic 0) is developed on a terminal and an abnormal" signal (logic 0) is developed on terminal 94. However, if the alarm contacts 20a changed from abnormal to normal, the record signal (logic 0) is again developed on terminal 94, and a normal signal (logic 1) is developed on the terminal 94.

A scanner generator circuit (FIG. 1), such as a 100 kilohertz relaxation oscillator, provides the count pulses for driving the scanner decoder circuit 88. The scanner counterdecoder circuit 88, in response to the count pulses, generates gating signals that are sequentially applied to the terminals Xl-Xn (FIG. 2) and enables or interrogates one select gate circuit 18 after another in consecutive order. The terminal 90 is connected to the scanner generator circuit 100 through an interlock circuit 102 to stop the generator circuit 100 when an interrogated select gate circuit indicates a change in status.

plete a counting cycle every 100 input pulses.

It should be understood of course that more or less contacts i 20a-20 may be used without departing from the invention. A gating circuit (not shown) is connected to the units counter so that a logic 1 is produced sequentially on l0 separate output circuits for each counting cycle. Similarly a gating circuit (not shown) is connected to the tens counter so that a logic 1 is produced sequentially on separate output circuit for each counting cycle. The output circuit of the units and tens gating circuits is connected to a matrix circuit (not shown) to select a different one out of a hundred output for sequentially applying the interrogation signals to the monitor circuits 2a2n in the input module 11 and interrogates the monitor circuits 2a-2n in rotation. When the scanner generator 100 is stopped by the recor signal on terminal 90, the units and tens counters hold a constant count corresponding to the monitor circuit 2a-2n indicating the change in status and keep the select gate circuit l8a-l8n enabled until the recording is completed on the display device 10.

The record" terminal 90 is also connected through the interlock circuit 102 to enable a baud counter 104 for initiating the record cycle. A baud generator or oscillator circuit 114 applies ll0 hertz count pulses to the baud counter 104 and also advance signals to a serializer circuit 115. The baud counter 104, when enabled by the record signal, completes a count cycle every 1 l pulses from the baud generator 114 to apply a carry pulse (10 characters per second) to a 13 count cycle character counter circuit 116.

The 13 possible positions of the character counter 116 are gated to a character decoder circuit 118 to produce a logic 1 on one of 13 output circuits according to the position of the character counter circuit 116. It should be understood that more or less counts can be included in the character counter circuit 116. The outputs from the character decoder 118 are labeled according to the position of the counter during the strobe interval whereby a logic 1 is produced. For example, the line labeled 8C3 indicates that a logic 1 is applied to the line during the position 3 of the character counter 116.

The line labeled SC8 applies a logic 1 from the character counter decoder 118 to the terminal V (FIG. 2) at the position 8 of the character counter 116. The logic 1 is inverted by an inverter circuit 106 (FIG. 2) to apply a logic 0 to the NOR gate circuit 82 in each of the memory circuits l8a-l8n. The other input circuit of the NOR gate 82 was previously enabled by a logic 0 from the NAND gate 86. The NOR gate 82 now applies a logic 0 to the NOR gate 62 which unlatches the memory circuit flip-flop (60,62) and allows the scanner counter decoder 88 to proceed after the recording has been completed. The interlock circuit 102 inhibits the scanner generator 100 while the flip-

flop circuit

60,62 is reset by way of line SC8. That is the flip-

flop circuit

60,62 is reset after the alarm point units (PAU) have been interrogated.

Once unlatched, the latch flip-flop circuit (60,62) can detect a subsequent change in the same alarm circuit or contacts a20n. With the flip-flop circuit (60,62) unlatched no record" signal is generated and therefore only a single recording is made of each change in status of the alarm contacts 20a-20n. A single recording such as time, contact identification and status provide the necessary alarm information.

It should be noted, although the flip-flop circuit (60,62) is unlatched during a recording cycle, a signal is still generated by the NOR gates 85 at the signal terminal 94 indicating the condition of the alarm contacts 20a-20n as the LII various monitoring circuits 2a-2n are interrogated. If a summary of the alarm circuits or contacts 20a-20n in the abnormal condition is desired, a logic 1 from a summary pushbutton circuit 120 is applied to the terminal U (FIG. 2) wherein the NAND gate 108 is enabled to apply a logic 0 to an input circuit of the NOR gate in all the memory circuits 16. If the connected alarm contacts 20a20n are in an abnormal condition, the other input circuit of the NOR gate 80 receives a logic 0 from the terminal 50 and therefore applies a logic 0 to the NOR gate 60 to latch" the memory circuit flip-flop (60,62). A record" signal is therefore generated for each monitor circuit 2 a-Zn to test the alarm contacts 20a20n for an abnormal or normal condition. The scanner decoder circuit 88 will therefore be stopped at each monitor circuit 2a-2n to observe an abnormal condition and to make a recording, regardless of whether or not a prior recording was made. A reset signal is applied to the inverter 106 during each recording as previously mentioned to disable the NAND gate 108 and apply a logic 0 to the NOR gate 82 to unlatch the flip-flop circuit (60,62) for the particular memory circuit l6a-l6n being recorded. As a result, only a single recording of each ab normal indicating monitor circuit 2a-2n is made each time a summary cycle is initiated.

A time generator circuit or oscillator 110, synchronized to the 60 hertz line mains, provides 60 hertz timing pulses to a digital time counter 112. If for any reason the 60 hertz input is interrupted, the time generator circuit 110 continues to operate at approximately 60 hertz for extended periods of time resulting in only a small error. The digital time counter 112 includes flip-flop circuits (not shown) which count down the pulses to second units, second tens, minute unit, minute tens, hour units and hour tens. When synchronized to the 60 cycle line mains, a counting cycle is completed every 24 hours. The digital time counter 112 provides the time information at the time of printout on the output display device 10.

A decoder circuit 122 is coupled to the baud generator 114 and the baud counter 104 to generate a strobe pulse in the order of several milliseconds every time the baud counter 104 reaches the count position three. The strobe pulse is applied to two

gate circuits

124 and 126 and also the serializer 115. The

gate circuits

124 and 126 are also coupled to the C2 and C 2 outputs of the second stage of the character counter 116 to apply strobe counting signals to the character decoder 118. The outputs from the eight counting stages of the character counter 116 are also applied to the character decoder 118.

The signals from the

gates

124 and 126 and from the character counter 1 16 are combined by the character decoder 118 to produce the control signals (SCO-SC12) for sequencing the presentation of variable and fixed information for loading in parallel into the serializer 115. The outputs of the

gates

124 and 126 are combined with the outputs from the character counter 116 so that the control signals SCl-8,10,1l and 12 have durations corresponding to the duration of the strobe pulses.

The time information from the digital time counter 112 is applied to a time encoder circuit 128. The output from the interlock circuit 102 and the output from the character counter 116 at the start of the count 8 through 12 are applied to the input of a NOR gate 87 to inhibit the time change of the digital time counter 112 whenever the baud counter 104 is enabled except during the character counts 8 through 12 (FIG. 5). The digital time counter 112 includes a flip-flop for storing a time change request from the time generator 110 until the absence of an inhibiting function from the NOR gate 87. The time generator 110 produces a time change request once every second. The alarm circuit identification information (scan position) from the scanner counterdecoder 88 is applied to a scanner encoder circuit 130. The signal terminal 94 (FIG. 2) is coupled to an A-N (abnormal-normal) encoder circuit 132.

A special function encoder 134 provides the signals for print control functions, such as, bell, space, return, line feed, etc. The output circuits of the

encoders

128, 130, 132 and 134 are coupled via a plurality of data lines for parallel loading the variable and fixed information into the serializer 115.

The

encoder circuits

128, 130, 132 and 134 are connected so that they are enabled by the output gating signals of the character counterdecoder 118. The encoder circuits define the display means functional circuits. The lines to the

various encoder circuits

128, 130, 132 and 134 are designated by sequential control signals (SCO-SCIZ) applied thereto. For example, the encoder 128 is enabled by the control signals SCO- corresponding to the first six counts of the character counter 116, to transmit the time data to the serializer 115. ln response to the control signals, information from the

encoders

128, 130, 132 and 134 is applied to the serializer 115, and the serializer is advanced by pulses from the baud generator 114 and marches information through an amplifier 140 to the output display device 10. The line labeled 8C3 between the character decoder 118 and the digital time counter 112 inhibits any time change when recording seconds. After an entire recording is completed, the baud counter 104 stops the character counter 116 to O causing the character decoder 118 to inhibit the baud counter 104 via line 142.

FIG. 5 is an illustration of the sequence of the information and control signals presented to an output display device as a function of the count positions of the character counter 116. The information is abbreviated in accordance to numerical order (0-12) as hours tens (HT), hours units (HU), minute tens (MT), minutes units (MU), second tens (T), second units (SU), space (SP), alarm tens (PAT), alarm units (PAU), status (N) normal or (A) abnormal (STA), return (RET), line feed (LF) and bell. When an alarm point (contact a-20n) changes status a recording cycle initiated as mentioned above and a 13 character message is initiated for recording an alphanumeric printout, one line per event, as illustrated below in Table I.

Table 1 Reading from left to right, the first six digits are for time in hours, minutes and seconds, a space, two digits for alarm point number and last status change. Thus the scanner decoder 88 resumes operation and both the baud counter 104 and the character counter 116 remain in the 0 count position until another change in state occurs in any one of the alarm contacts 20a20n.

The NOR gate 85 in the select gate circuits l8a-18n (FIG. 2) provides an output signal corresponding to the last event that occurred just prior to printout which in this particular case would be an N (normal) type signal.

The recording consumes a modest amount of paper, even when recording lengthy sequences of changes. The alphanumeric printout is easy for an operator to interpret. For example the top row indicates at 11 hours, 12 minutes and 31 seconds, alarm contact 3 changed from normal (N) to abnormal (A). The second row indicates that at l 1 hours, 23 minutes and 34 seconds, alarm 5 changed from abnormal (A) to normal (N). As an example, it is possible that an alarm contact may change from normal to abnormal and back to normal during the recording of a prior alarm or event. In such case, a recording will still be made despite the number of changes in status. This is due to the fact that the flip-flop circuit (60,62) in the memory circuits (1611-1611) is latched" and remains in this state until unlatched" by a printing in a manner as heretofore mentioned. This condition can be readily interpreted by an operator by scanning the previous recordings for any prior change in the same alarm point. Accordingly it can be seen, as long as there has been a change in status, there will be a recording.

The events recorder of the invention can readily monitor a large number of alarm circuits, transducers or contacts. The alarm circuits or contacts can either be open or closed during a normal operating condition. A readily readable alphanumeric printout is provided to indicate hours, minutes, seconds, point identity and point status followed by an audible bell signal. The first-to-alarm circuit is recorded first, followed by alarm points in scanning order. However, if the time difference between alarms is greater than required for printout, the alarms will be recorded in a time of occurrence sequence. Only a single recording of a change of status is made, however a printout of all abnormal points can be made by initiating the summary mode of operation.

While there has been described one specific embodiment of the invention for purposes of illustration, it is contemplated that numerous changes may be made without departing from the spirit of the invention.

What is claimed is:

1. A circuit for indicating a change in the status of an alarm circuit comprising:

a. switching means responsive to a change in the status of said alarm circuit for providing a series of signal pulses,

b. bistable circuit means having first and second input circuits for switching into first and second modes of operation respectively,

c.a reactive circuit coupling said switching means to said first input circuit for switching said bistable circuit means into said first mode of operation in response to said signal pulses for indicating a change in status of said alarm circuit, and

d. circuit means coupled to said second input circuit for switching said bistable circuit into said second mode of operation for conditioning said bistable switching means to indicate a subsequent change in status of said alarm circuit.

2. The invention defined in claim 1 wherein:

said alarm circuit has a first and a second status of operation; and

said switching means is coupled to said alarm circuit to produce said series of pulses each time said alarm circuit switches between said first and second status of operation.

3. The invention defined in claim 1 wherein:

said switching means is an electromechanical device having at least one normally open electrical contact which exhibits contact bounce when closing to provide said series of pulses.

4. The invention defined in claim 1 wherein:

said bistable circuit means requires direct current signals on said first and second input circuits to switch modes of operations, and

said reactive circuit charges to a sufficient magnitude in response to said series of pulses to switch said bistable circuit means into said first mode of operationv 5. The invention defined in claim 1 wherein:

said bistable circuit includes a pair of NOR gates coupled to fonn a flip-flop circuit.

6. The invention defined in claim 1 wherein:

said reactive circuit includes a capacitor which charges to a voltage sufficient to switch said bistable circuit into one of said first and second modes of operation in response to said series of pulses.

7. In an events recorder for indicating a change in state of an alarm circuit having one state when normal and a second state when abnormal, the combination comprising:

a. a source of direct current voltage,

b. relay means including a coil connected in circuit with said alarm circuit and normally open resonant contacts connected to said source representing one. state of said alarm circuit when open,

0. said contacts bounce upon closure to produce a varying direct current voltage representing said other state of said alarm circuit,

a bistable circuit means having first and second input circuits for switching into first and second modes of operation respectively for indicating said change in state of said alarm circuit,

. a reactive circuit means coupling said relay means to said first input circuit for switching said bistable circuit means into said first mode of operation in response to said varying direct current voltage, and

. circuit means coupled to said second input circuit for switching said bistable circuit into said second mode of first and second modes of operation in response to said varying direct current voltage.

Claims

1. A circuit for indicating a change in the status of an alarm circuit comprising: a. switching means responsive to a change in the status of said alarm circuit for providing a series of signal pulses, b. bistable circuit means having first and second input circuits for switching into first and second modes of operation respectively, c. a reactive circuit coupling said switching means to said first input circuit for switching said bistable circuit means into said first mode of operation in response to said signal pulses for indicating a change in status of said alarm circuit, and d. circuit means coupled to said second input circuit for switching said bistable circuit into said second mode of operation for conditioning said bistable switching means to indicate a subsequent change in status of said alarm circuit.

2. The invention defined in claim 1 wherein: said alarm circuit has a first and a second status of operation; and said switching means is coupled to said alarm circuit to produce said series of pulses each time said alarm circuit switches between said first and second status of operation.

3. The invention defined in claim 1 wherein: said switching means is an electromechanical device having at least one normally open electrical contact which exhibits contact bounce when closing to provide said series of pulses.

4. The invention defined in claim 1 wherein: said bistable circuit means requires direct current signals on said first and second input circuits to switch modes of operations, and said reactive circuit charges to a sufficient magnitude in response to said series of pulses to switch said bistable circuit means into said first mode of operation.

5. The invention defined in claim 1 wherein: said bistable circuit includes a pair of NOR gates coupled to form a flip-flop circuit.

6. The invention defined in claim 1 wherein: said reactive circuit includes a capacitor which charges to a voltage sufficient to switch said bistable circuit into one of said first and second modes of operation in response to said series of pulses.

7. In an events recorder for indicating a change in state of an alarm circuit having one state when normal and a second state when abnormal, the combination comprising: a. a source of direct current voltage, b. relay means including a coil connected in circuit with said alarm circuit and normally open resonant contacts connected to said source representing one state of said alarm circuit when open, c. said contacts bounce upon closure to produce a varying direct current voltage representing said other state of said alarm circuit, d. a bistable circuit means having first and second input circuits for switching into first and second modes of operation respectively for indicating said change in state of said alarm circuit, e. a reactive circuit means coupling said relay means to said first input circuit for switching said bistable circuit means into said first mode of operation in response to said varying direct current voltage, and f. circuit means coupled to said second input circuit for switching said bistable circuit into said second mode of operation for conditioning said bistable switching means to indicate a subsequent change in the state of said alarm switching circuit when said resonant contacts open.

8. The invention defined in claim 7 wherein said reactive circuit means includes a capacitor which charges to a voltage sufficient to switch said bistable circuit means into one of said first and second modes of operation in response to said varying direct current voltage.