KR900001335B1 - System console automatic testing system of electronic exchange - Google Patents

Abstract

The apparatus for displaying the test response data as well as transmitting the data respective to the test condition for each function of the system console includes a start/reset dircuit (10) for generating the initialising signal and clock pulse, an address signal generator (20) for providing the step running data and address, a step displaying circuit (30) for displaying the present test running state, a reference and test data output circuit (40) for providing the reference signal to a discriminating circuit (60) as well as the test data to the system console through a transmitting level converter (50).

Description

System console automatic tester of electronic exchange

1 is a block diagram of a conventional system console automatic test apparatus.

2 is a block diagram according to the present invention.

3 is a detailed circuit diagram of an embodiment of FIG.

* Explanation of symbols for main parts of the drawings

10: start / reset circuit 20: address signal generation circuit

30: step display circuit 40: reference and test data output circuit

50: Transmit level converter 60: Judgment display circuit.

The present invention relates to an automatic test system for the system console, which is a monitoring and warning device of an electronic exchange. In particular, the system can automatically display data on the test conditions of each function of the system console and at the same time accurately display the function test response data. The present invention relates to a system control automatic test apparatus for an electronic exchange.

In general, the system console of an electronic exchange is an alarm, automatic superviser (ATS), automatic answer trunk (ATT), and marking maintenance line of the local and other electronic exchanges according to a predetermined program. And diode alarm

The conventional electronic switch system console automatic test apparatus having the above-mentioned functions includes a switching data output circuit (1) for outputting test data by manual switching operation as shown in FIG. 1, and the switching data output circuit (1). Buffer 2 for buffering and outputting the test data outputted from the control panel, a time setting circuit 3 for adjusting and supplying the test data supply time, and the switching data output circuit 1 and the time setting circuit 3 The decoder 4 inputs and decodes the test data and the time setting signal respectively output, and the test data supply signal (Test order) output from the buffer 2 is temporarily stored and decoded by the decoder 4. A RAM 5 for outputting test data, a voltage level converting circuit 6 for converting and outputting a test supply signal (Test order) output from the RAM 5 to a corresponding test voltage level, and the RAM (5) Standing by entering the result signal output from the test signal supplied to the system console for outputting test data was composed of a display device (7) for displaying test results by entering the test results.

The circuit operation configured as described above is as follows. The test data output from the switching data output circuit 1 outputting the test data by the manual operation switching operation is temporarily stored in the RAM 5, which is a test data temporary storage device, via the buffer 2 and at the same time in the decoder 4 Is entered.

At this time, when the test data output time is set in the time setting circuit 3 by manual operation, the time setting circuit 3 outputs the set time data to the decoder 4.

The decoder 4 which inputs the test data and the setting time data output from the switching data output circuit 1 and the time setting circuit 2, respectively, decodes the test data input at the set time to test data supply time setting data. Is output to the RAM (5).

Therefore, the RAM 5 temporarily storing the test data input through the buffer 2 accesses the test data stored while the test data supply time setting data outputted from the decoder 4 is inputted, thereby providing test signal supply data (Test order) is outputted to the voltage level converting circuit 6 and the test data display device 7. The voltage level converting circuit 6 inputting the test signal supply data output from the RAM 5 is converted to the corresponding voltage level and supplied to the system console (not shown). That is, the voltage level converter 6 converts the test signal supply data of + 5V to -48V level, which is the transfer voltage level of the exchanger, and transmits the data level to the system console (not shown).

At this time, the system console inputs the test signal supply data of the level conversion output from the level conversion circuit 6 to test a function corresponding to the input signal, and then sends the test response data through the terminal 8 to the test data display device 7. Will output

In addition, the test data display device 7 which inputs the test signal data output from the RAM 5 and the response data output from the system console displays the tested result status.

However, in the conventional system console test apparatus operated as described above, the test signal data is not correctly input by the check by the manual operation of the tester, and an error occurs due to the test result check light due to the lighting of the lamp of the test data display apparatus 7. There was a problem. Especially current

Therefore, an object of the present invention is to automatically send a test signal supply data corresponding to the test conditions of each function of the system console to automatically display the system console response signal to test the system console automatic tester of the electronic exchanger In providing.

Another object of the present invention is to provide a circuit that can continuously test the function of the system console and display the current progress.

In order to achieve the above object, the present invention provides a system console automatic test apparatus for an electronic exchanger having a transmission level converter which inputs a test signal supply data, converts the voltage into a corresponding voltage level, and transmits the test initialization signal. A start / reset circuit for generating a clock pulse of a predetermined period, an address signal generator for counting the clocks of the predetermined period, outputting step progress data and generating an address signal, and a step progress outputting the address signal generator; A step display circuit which input-decodes data to display a current progress state, and stores reference data and test signal supply data, and inputs an address signal output from the address signal generator and outputs corresponding reference data at the same time. Access signal supply data Determining whether or not the reference and test data output circuit outputted to the system console through the transmission level converter and the reference data of the reference and test data output circuit and the response data provided from the system console are displayed and then displayed. Characterized in that it comprises a display circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram according to the present invention, which comprises a start / reset circuit 10 for outputting an initialization signal at the start of a test and generating and outputting a clock pulse of a predetermined period according to the start signal, and a clock pulse of the predetermined period. An address signal generation circuit 20 for counting and outputting step progress data and generating an address signal, and a step display circuit for inputting and decoding the step progress data output from the address signal generation circuit 20 to display a current progress state; A reference and test data output circuit 40 which stores reference data and test signal supply data and accesses them according to the address signals output from the address signal generating circuit 20; Song that inputs the test signal supply data output from the data output circuit 40, converts it to the corresponding transmission level, and outputs Judgment display for displaying normal presence or absence by comparing the actual level converter 50, the reference data output from the reference and test data output circuit 40, and the response data output from a system console (not shown). It is characterized by consisting of a circuit (60).

After generating and outputting an initialization signal from the start / reset circuit 10, a clock pulse necessary for test execution is generated and output as an address signal generation signal 20. The address signal generation circuit 20 is initialized after The clock pulse is counted to output step progress data to the step display circuit 30, and the address signal counted to the clock pulse is output to the reference and test data output circuits 40.

At this time, the step display circuit 30 that inputs the step progress data output from the address signal generation circuit 20 decodes the step progress data and displays a current function test process. In addition, the reference and test data output circuit 40 inputting the address accesses the reference data and the test signal supply data of the address designated by the address signal from the internal memory.

The transmission level converter 50 which inputs the test signal supply data output from the reference and test data output circuit 40 converts the test signal supply data of the 5V level into a voltage level of -48V required for the system console. ) To the system console.

The system console which inputs test signal supply data output from the transmission level converter 50 tests each function and outputs test response data which is a test result of the test signal supply data to the terminal 200. At this time, the test response data is the result data after the system console performs a test corresponding to the input test signal supply data. For example, if RTF test data is output from the reference and test data output data, the system console performs the MFC (Multi Frequency Code) regular test of the system and then represents the test result.

Meanwhile, the judgment display circuit which inputs the reference data output from the reference and test data output circuit 40 and the response data of the system console inputted to the terminal 200 has been tested in the system console after comparing the reference data and the response data. Displays the normal presence or absence of the.

Therefore, a plurality of test signal supply data and reference data of the system console in the reference and test data output circuit 40 described above, for example, ALM, ATS, AAT, AMD, SPP, CPG, RTC, RTD, RTF, AALI, TTT If you save test data and standard data to test the functions of the system, you can automatically test various functions of the system console.

FIG. 2 is a specific circuit diagram of one embodiment of the block diagram of FIG. 1, which generates an address signal composed of a start / reset circuit 10, a first counter 21, and a second counter 22. FIG.

Hereinafter, an operation example of FIG. 3 according to the present invention will be described in detail.

When the test start key (not shown) is pressed now, the start / reset circuit 10 generates a clock pulse of a predetermined period immediately after outputting the reset signal to generate the first counter 20 and the second counter. Output to the counter 30.

The reset signal generated by the start / reset circuit 10 and the first and second counters 21 that input the clock signal are initialized and then count the clock pulses counting the clock pulses. And output to the ROMs 42 and 43. At this time, the first counter 21 counts the data output from the start reset circuit 10 and outputs the data as step progress data, and the second counter 22 outputs the address data.

The decoder 31 that inputs the step progress data output from the first counter 20 decodes the counting data and outputs the step progress data to the binary BCD code converter 32.

At this time, the binary BCD code converter 32 which inputs the decoded step data converts the step data of the binary signal into the BCD code and outputs it to the first display device 33 composed of 7-segments, and converts it into the BCD code. The first display device 33 which has input the completed step progress data is currently in progress.

On the other hand, the ROMs 42 and 43 which input the address data output from the two counters 22 access the reference data and the test signal supply data designated by the address data, respectively, and compare the circuit 61 and the transmission level converter 50. )

The time adjustment circuit 41 outputs time setting data to the ROM 43 for adjusting the test signal supply data output time.

Therefore, the ROM 43 inputting the address signal output from the second counter 22 and the time adjustment signal output from the time adjustment circuit 41 outputs the test signal supply data of the address designated by the address signal. In accordance with the time control signal output from the output to the transmission level converter 50.

At this time, the transmission level converter 50 inputting the test signal supply data output from the ROM 43 converts the test signal supply data of + 5V to the system console input voltage level of -48V, and then through the terminal 100, the system console ( (Not shown).

For example, if the test signal supply data and the reference data for testing ALM, ATS, AAT, AMD, SPP, CPG, RTC, ALIR, TTT, etc. in the ROM 43 and 42 are stored for each predetermined area, Access is sequentially output by the counting data of the second counter 22. That is, the test data and the reference data stored in the predetermined areas of the ROMs 43 and 42 are sequentially accessed by the address data output from the second counter 22 and compared with the transmission level converter 50 as described above. Supplied to the circuit 61.

The system console which inputs the test voltage level test signal supply data outputted from the transmission level converter 50 tests the function corresponding to the test signal supply data, and

In addition, the reception level converter 62, which inputs the response data output from the system console, converts the input response data (result data after the functional test) input at the level of -48V to the reception level of + 5V to compare the circuit 61. Enter

The comparison circuit 61 inputs the response data converted by the reception level converter 62 to the TTL level at which the response data is the reception level and the reference data output from the ROM 42 described above. Comparing the response data, and outputs the data of the normal or not function monitored by the system console to the second display device (63). * The second display device 63 inputting the presence / absence of the data output from the comparison circuit 61 displays whether the current function test state is normal.

Therefore, as described above, the present invention automatically transmits the test signal supply data stored in the ROM as a start signal, so that all tests of the system console are automatically performed, and at the same time, the state of the ongoing test and the test result state are easily displayed. The advantage is that you can test the system console.

Claims (1)

A system console automatic test apparatus for an electronic exchange having a transmission level converter (50) for inputting test signal supply data of a predetermined level, converting the system signal to a test voltage level, and transmitting the initialization signal by inputting a start key signal. Generating a step progress data and an address signal by counting a start / reset circuit 10 that generates clock pulses of a predetermined period and a predetermined period of clock pulses output from the start / reset circuit 10. An address generation circuit 20, a step display circuit 30 for decoding the step progress data output from the address signal generation circuit 20 into display data and displaying a current test progress state, various test signal supply data and Reference data corresponding to the test signal supply data are stored and output from the address signal generating circuit 20. Accesses the stored reference data and the test signal supply data for a predetermined time by an address signal, outputs the reference data to the judgment display circuit 60, and simultaneously transmits the test signal supply data through the transmission level converter 50. After comparing the standard and test data output circuit 40 to transmit the system console with the reference data output from the reference data and test signal data output circuit 40 and the response data output from the system console, And a decision display circuit (60) for displaying the result status.

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