SU1691954A1 - Reserved frequency divider - Google Patents

Abstract

The invention relates to a pulse technique and can be used in constructing time keepers of increased reliability. The purpose of the invention is the expansion of the range of the output pulses, which is achieved by introducing the first, second and third control units 16, 17 and 18, as well as the fact that the control unit contains the first and second half adders, the delay element, the coincidence element and the D-flip-flop. The device also contains the first, second and third frequency division channels 1-3, each of which contains a counter of 4 pulses, a coincidence element 5 and an element OR 6, the first, second, third input buses 7, 8, 9, first, second, third major elements 10, 11, 12, first, second, third output tires 13, 14, 15. 1 c.p. f-ly, 5 ill.

Description

The invention relates to a pulse technique and can be used in the construction of time savers of increased reliability.

The purpose of the invention is to expand the range of the output pulse duty cycle.

FIG. 1 shows the electrical structural diagram of the device; in fig. 2 - electrical circuit of the control unit; Fig. 3 shows timing diagrams explaining the operation of the device; in fig. 4 - timing diagrams explaining the operation of the control unit; in fig. 5 - timing diagrams explaining the operation of the device in the mode of self-synchronization.

The redundant frequency divider contains the first, second and third frequency division channels 1-3, each of which contains a counter 4 (4 1, 4 2. 4 3) pulses, an element 5 (5.1, 5.2, 5.3) coincidence and an element

OR 6 (6.1, 6.2, 6.3). The clock input (C input) of the counter 4.1 pulses of the first frequency division channel 1 is connected to the first input bus 7, the clock input (C input) of the counter 4.2 pulses of the second frequency channel 2 2 is connected to the second input bus 8, clock (C- input) of the counter 4.3 pulses of the third frequency division channel 3 is connected to the third input bus 9. The output of the first major element 10 is connected to the pin output bus 13, the output of the second major element 11 is connected to the second output bus 14, the output of the third major element 12 is connected to the third out one bus 15.

The divider also contains the first, second and third blocks 16-18 of the control, the first and second inputs of each of which are connected respectively to the same input and the output of the corresponding majority

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element 10, 11 and 12. In each of the channels 1,2,3 frequency division, the reset inputs (R-inputs) of the pulse counters 4 are connected to the outputs of the coincidence elements 5, the first and second inputs of which are connected respectively to the outputs of the corresponding blocks 16 18 controls and with the outputs of the corresponding elements OR 6, the first and second inputs of which are connected to the outputs of the counters 4 pulses of adjacent frequency division channels, The outputs of the counters4 pulses of the first, second and third channels 1-3 of the frequency division are connected to single-input inputs respectively , Second and third elements 16-18 majority.

Each of blocks 16, 17, 18 controls contains the first and second half-adders 19,20, delay element 21, the match element 2И-НЕ 22 and D-flip-flop 23. The first inputs of the half-adders 19, 20 are connected to the first input of the control unit, as well as to the clock the input (C-input) of the D-flip-flop 23. The second inputs of the half adders 19, 20 are connected to the second input of the control unit. The setup input (S-input) of D-flip-flop 23 is connected to the output of coincidence element 2И-НЕ 22, the first run of which is connected via delay element 21 to the output of the first half-accumulator 19, and the second input - to the output of the second half-adder 20. Output of the D-trigger 23 connected to the output of the control unit, and its D-input is connected to the common bus. It should be noted that one half-adder can be used in the control unit (with the corresponding load capacity).

The divider works as follows.

Tires 7, 8, 9 receive input pulses. From buses 7, 8, 9, the input pulses arrive at the clock inputs of counters 4 of the first, second and third channels 1, 2, 3. Under the action of the input pulses, counters 4.1, 4.2, 4.3 are filled. When the counter is filled, an impulse log is formed at its output. 1 with the duration tM (FIG. Pro, b, c). In this case, the duration tn of the pulse generated at the output of counter 4 can be substantially less than the duration Tn of the period of their repetition, i.e. Ty "Tp.

From the outputs of channels 1, 2, 3, pulses arrive at the corresponding inputs of elements 10–12. In accordance with the majority function of elements 10, 11, 12, the appearance of pulses of a log. 1, at the inputs of the majority elements (Fig. Za, b, c), pulses of a log appear at their outputs. 1 with a delay of gm determined by the time of passage of the signal log. 1 through

the majority element (Fig. Zg, d, e), while um so-called.

From the outputs of the elements 10, 11, 12 pulses of the log. 1 (Fig. 3g, d, e) are fed to the corresponding output buses 13, 14 15 of the device.

From the output of each of the channels 1, 2, 3. impulses log. 1 also arrive at the first input of the corresponding block 16, 17, 18

0 control, the second input of each of which receives pulses from the outputs of the respective majority elements 10, 11, 12.

In each of the blocks 16, 17, 18 impulse

5 log. 1 from the output of the corresponding frequency division channel is fed to the first inputs of the adders 19, 20, to the second inputs of which a pulse log arrives with a delay of Tm. 1 from the output of the corresponding majority

0 element (Fig. 4a, b). (For the sake of clarity, the scale along the t axis in Fig. 4 is enlarged compared with Fig. 3). When exposed to pulses log. 1 (Fig. 4a, b), shifted relative to each other by the time um, two pulses of the log are formed at the outputs of half-sums of maters 19, 20. 1, with a duration of TM, separated from each other by time g - m (Fig. 4c, d). A pair of pulses thus generated from the output of the half adder 19 is fed to

0 the input of the element 21, where it is delayed by the time T3, where tm T3 t ' is tm (Fig. 4e). With the release of the element 21 delayed pulses log. 1 (Fig. 4e) arrive at the first inlet - of element 22, on the second EXIT

5 which receives impulses log. 1 (Fig. 4d) from the output of the half adder 20. Since the coincidence of the pulses of the log. 1 is not present at the inputs of element 22 (Fig. 4d, d), then the output of element 22 is stored in a log. 1 (Fig. 4e). Signal log. 1, arriving at the setup input of the D-flip-flop 23 from the output of the element 22, does not change the zero state of the D-flip-flop 23 (Fig. 4g), periodically confirmed by pulses coming from the first input of the frequency division control unit to the clock input D- trigger 23.

From the output of the D-flip-flop 23 log, 0 is fed to the output of the control unit of the frequency division channel.

0 Thus, during normal operation of the device from the outputs of each of the blocks 16, 17, 18 signals with the level of the log. О (fig. Зж, з, и) are fed to the first inputs of the elements 5 of the corresponding 5th division channel. In this case, the second inputs of elements 5 receive pulses of the log. 1 (Fig. G3, h, m) from the outputs of elements 6. Since the first inputs of elements 5 permanently contain a log. O (Fig. 3, 3, 3) the log is saved on their outputs. 1 (Fig. Zn, o, p). From the outputs of the elements 5.1, 5x2, 5.3 log. 1 (Fig. 3n, o, p) are fed to the R-inputs (reset inputs) of pulse counters 4.1, 4.2,4.3, not preventing them from being counted under the influence of input pulses arriving at their clock inputs.

In the case of a failure in the counter of one of the channels, for example, in the counter 4.1 of channel 1, at the time of time n (Fig. 3g), when the output of element 10 is a log signal. Oh, the counter 4.1 continues counting pulses, albeit an erroneous one, as a result of which at the time t2 at its output an erroneous impulse log is formed. 1 (FIG. 3a), which arrives at the first input of element 10. At the same time, at the output of element 10, at the first input of which the indicated erroneous impulse arrives, the correct impulse is formed at the time t.c (fig. 3g) due to impulses to its second and third inputs from the outputs of healthy channels 2 and 3 (Fig. 36, c). Thereby, reservation of a downlink channel is performed.

Then synchronization of the downed channel is performed. This synchronization is carried out with the help of a corresponding block of the frequency division channel, in particular, in the case under consideration, with the help of block 16. The operation of block 16 of the first frequency division channel occurs in this case as follows.

When the indicated erroneous impulse from the output of the counter 4.1 to the first inputs of the half adders 19, 20 (Fig. 4a) arrives at their outputs, a log is generated. 1 with a duration equal to the duration of the input pulse (Fig. 4c, d). These pulses arrive at the inputs of element 22, and the pulse from the output of the half-adder 19 is with a delay of m3, where gm te ti is TM, tm ti (Fig. 4e). As a result of a matching log. 1, at the inputs of element 22, at the output of element 22, a pulse log is generated. About the duration of t 1I - e (Fig. 4e). Impulse log About comes from the output of the element 22 to the installation input of the D-flip-flop 23 and sets at its output the level of the log. 1 (Fig. 4g). This level does not change from the impulse arriving at the second input of block 16 at the moment of time ts (Fig. 46, c, d, e, f, g). The log level thus set. 1 at the output of the D-flip-flop will exist until the next pulse is received by the first input of block 16. 1 from the output of the counter 4.1, which with its front sets the D-grigger to the state of log 0, i.e. up to the moment i (fig. 4a, g).

Signal level log. 1 (Fig. 4g, Зж) from the output of block 16 is fed to the first output 5 of the element 5.1 of the downed channel 1. The second input of the element 5.1 is given a pulse log. 1 (Fig. G3), formed at the output of element 6.1 as a result of the impact of pulses log. 1 coming from the outputs

0 serviceable channels 2, 3 (Fig. Sv, b), If there is a log. 1 at the inputs of the element 51 2I-NOT (Fig. Зж, к) at its output the level log, 1 changes to the level log. Oh, thereby forming a pulse log. Oh, the duration of gi (Fig. 3N). On the front of the pulse log. 0, coming from the output of element 5.1 to the R input of the counter 4.1 of pulses of a downed channel, the latter is set to its original position. Since the front of this pulse is attached to the pulse fronts at the outputs of counters 4.2, 4.3 (Fig. 36, b, n), thus the confused 4.1 counter is synchronized with the counters 4.2, 4.3 of the service channels.

5 In this way, the synchronization of downed channel 1 is performed, and the maximum synchronization time Atc of the downed frequency dividing channel does not exceed the repetition period of its output pulses.

If one of the channels completely fails (when the output of counter 4 freezes in any position — log. O or log. 1), the signals on the output buses are formed

5 at the expense of the other two working channels, thereby making the reservation of the channels.

Let us consider the features of the self-synchronization process on the example of the device operation after the supply of the supply voltage to it. Since when the device is turned on, the counters 4.1, 4.2, 4.3 can be set to an arbitrary position, the signals at the inputs of the elements 10, 11, 12 may not

5 coincide in time, as a result of which the signals at the outputs of the majority elements may be absent. In this case, the first inputs of the control units of the frequency division channels i will receive pulses only from

0 outputs of pulse counters of the corresponding channels. The processes occurring in the blocks of control of the frequency division channels under the considered conditions of the impact of pulses arriving at only one (first) of its input are similar to the processes described above that occur when the channels fail (see Fig. 3, 4, the sections corresponding to time t2 st 1.3). As in the case described above, the considered situation of the impact of pulses only on the first input of the control units of the frequency division channels will lead to the formation at the outputs of the control units of the frequency division channels signals of a constant level log. 1, providing the ability to synchronize channels relative to each other.

Consider a conditional example, when at the output of the first channel a pulse log. 1 after the device is turned on earlier than at the outputs of the second and third channels, and at the output of the second channel earlier than at the output of the third channel (Fig. 5a, b, c). In this case, under the influence of these pulses level log. 1 from the output of block 16 to Wits before log. 1 from the output of block 17, and from the output of block 17 earlier than from the output of block 18 (Fig. 5, h, i). Signal level log. G from the output of block 16 (Fig. 5g) is fed (first in time) to the first input of the matching element 5.1 of channel 1, then to the second input of the element 5.1 through element 6.1 receives a pulse log. 1 (Fig. 5k) from the output of channel 2 (Fig. 56), under the action of which a log is generated at the output of element 2–– 5.1. O (Fig. 5c). On the front of the pulse log. O (Fig. 5n), the counter 4.1 is set to the initial position, corresponding to the initial position of the counter 4.2 of channel 2 (determined by the front of its output pulse, Fig. 56). In this case, the pulse log. 1 at the output of channel 2 (similar to channel 1 discussed above) results in the appearance (with a delay of G3) of a level log. 1 at the output of block 17 (FIG. 5z), which arrives at the first input of element 5.2 of channel 2. Then, to the second inputs of elements 5.1 and 5.2 of channels 1 and 2, pulses are received through the corresponding elements 6.1 and 6.2. 1 (Fig. 5k, l) from the output of channel 3 (Fig. 5c). Since at the first inputs of elements 5.1 and 5.2 there is a log. 1, coming from the outputs of blocks 16 and 17 (Fig. 5g, h), then under the action of impulses, in the log. 1, arriving from the outputs of elements 6.1 and 6.2 (Fig. 5k, l), a log is generated at the outputs of elements 5.1 and 5.2. O (Fig. 5n, o). On the front of these pulses log. O (fig. 5n, o) the counters 4.1 and 4.2 are set to the initial position, corresponding to the initial position of the counter 4.3 of channel 3 (determined by the front of its output pulse, fig. 5c).

From this point on, all three frequency division channels start to operate synchronously and after a time equal to the period Tn, the outputs of the devices 10, 11, 12 appear in the output of the counters 4.1, 4.2, 4.3, and then the device output pulses appear at the outputs of elements 10, 11, 12 (Fig. 5d , d, e).

Claims (2)

1. The reserved frequency divider containing the first, second and third frequency division channels, each of which contains a pulse counter and a matching element, the output of which is connected to the reset input of the pulse counter, and the clock inputs of the first, second and third channel pulse counters are connected respectively with the first, second and third input buses; the outputs of the pulse counters of the first, second and third frequency division channels are connected to the same inputs of the first, second and third major elements, respectively, whose outputs are connected to the first, second and third output buses, respectively, that, in order to expand the range of the output pulses' duty cycle, the first, second and third control units are entered into it, the first and second inputs of each of which are connected respectively to the same name the input and output of the corresponding major element, the outputs with the first inputs of the matching elements of the corresponding frequency division channels, each of which has an OR element, the output of which is connected to the second input of the coincident element, the first and second inputs connected to the outputs of the pulse counters of the other frequency division channels . 2. A divider according to claim 1, characterized in that the control unit contains the first and the second half-adders, the delay element, the match element and the D-flip-flop, the first inputs of the half-adders are connected to the first input of the control unit and to the clock input of the D-trigger, the second inputs half accumulators are connected to the second input of the control unit, the setup input of the D-trigger is connected to the output of the coincidence element, the first input of which is connected through the delay element to the output of the first half-adder, and the second input of the coincidence element is connected to the output of the second half-adder, and the information input of the D-trigger is connected with shared bus five Fa Z