SU1195489A1 - Redundant device for synchronizing - Google Patents

Abstract

A RESERVED DEVICE FOR SYNCHRONIZATION, containing in each of the three channels series-connected master oscillator, first counter and first decoder, serially connected first element I, second counter, second decoder, as well as delay element, element ZI-NO, high-frequency generator and single-oscillator, different so that, in order to increase reliability and testability, an anchor block, a control block, two voltage dividers, a disconnect element, two Schmitt triggers, five elements are inserted into each channel. And, zeroing bus, OR-NOT element and OR element, the output of which is connected to the one-shot input, the first input - to the output of the second element AND, the second and third inputs - to the outputs of the third and fourth elements, respectively, the first inputs of which are connected respectively to the first and second exchange inputs, the second inputs, respectively, with the third and fourth exchange inputs, as well as the first inputs, respectively, of the fifth and sixth And elements, the outputs of which are connected respectively to the first and second inputs of the rety input is connected to the output of the control unit; the output is connected to the first input of the second element I, the first exchange output and the first input of the anchor block, the second input of which is connected to the output of the delay element, the output to the installation input of the first counter and the first input of the control unit, the second the input of which is connected to the output of the high-frequency generator, the third input to the output of the first decoder, the second pass of the second element AND and the second exchange output, the fourth input to the nulling bus and the output of the isolation element, output dyes (L of which are connected respectively to the fifth and sixth exchange inputs and inputs, respectively, of the first and second Schmitt triggers, the outputs of which are connected to the second inputs of the fifth and sixth elements, respectively, the outputs of the first and; o and the second voltage divider are connected respectively to the third and fourth exchange outputs, while the first and second exchange outputs of the first channel are connected, respectively, with the third and first exchange inputs of the second, and also the fourth and second exchange ports the third and fourth exchange inputs, respectively, with the fifth and sixth exchange inputs of the second and third channels, respectively, the exchange outputs of which are connected to the corresponding exchange inputs of the first and third, as well as the first and second channels, respectively.

Description

The invention relates to computing and automation and can be used to build control systems with increased reliability.

The purpose of the invention is to increase the reliability and testability of the device.

FIG. 1 shows a block diagram of the device; in fig. 2-4 - structure of the anchor unit, the control unit, the frequency meter, respectively; in fig. 5-7 are diagrams of temporary device diagrams; in fig. 8 - transfer characteristic of Schmitt trigger.

The device (Fig. 1) contains in each channel the first element I 1 serially connected, counter 2, decoder 3 and delay element 4, element ZI-HE 5, the first input of which is connected to the output of delay element 4, the output to the first input of element AND 1, a high-frequency generator 6, the output of which is connected to the second inputs of the elements I 1 and ZI-HE 5, the one-shot 7, the output of which is connected to the third input of the element ZI-HE 5, the series-connected oscillator 8, counters 9 and the decoder 10, the control unit 11, second 12, fifth 13, sixth 14, third 15 and the fourth 16 AND elements, the OR elements OR 17 and OR-NOT 18. The binding unit 19, the first input 20 of which is connected to the output of the IL-NOT 18 element, the first input of the AND 12 element and the exchange output 21, the second input 22 - from the output the delay element 4, the output 23 - with the installation input of the counter 9 and the input 24 of the control unit 11 (the output 59 of the anchor block 19 is not used), the input 25 of which is connected to the output of the high-frequency generator 6, the input 26 - to the output of the decoder 10, exchangeable output 27 and the second input element And 12, output 28 - with the third input element OR NOT 18, the first and second the inputs of which are connected to the outputs of the elements 13 and 14, respectively, the first inputs of which are connected to the exchange inputs 29 and 30, respectively, as well as the second inputs of the elements 15 and 16, respectively, the first inputs of which are connected to the exchange inputs i1 and 52 respectively 954892

The outputs are with the reverse and second inputs of the element OR 17, the third input of which is connected to the output of the element AND 12, the output to the input of the one-vibrator of torus 7, zeroing bus 33, isolation element 34, Schmitt triggers 35 and 36, whose inputs are connected to the second inputs 37 and 38 of the channel, respectively, as well as with the outputs of the element 34

10 wiring, the input of which is connected to the zero line 33 and the fourth input 39 of the control unit 11, as well as the voltage dividers 40 and 41. In this case, the exchange outputs 21 and 27 of the first channel

15 are connected respectively to the exchange inputs 29 and 31 of the second, and also respectively to the exchange inputs 30 and 32 of the third channel, exchange outputs 42 and 43 with the exchange input 38 of the second

20 and the exchange input 37 of the third channel, respectively, whose exchange inputs are connected in the same way. The output 44 of the device is the output of any bit of counter 2,

25,

The anchor block 19 (Fig. 2) contains a shift register 45 containing serially connected 1K-flip-flops 46 - 48, inputs C of which soy-Q are connected to each other and form a clock input 49 of the shift register 45, as well as an inverter 50 whose output is connected with the input To, the input with the input of the trigger 46, forming the shift input 51, the shift register 45,

 the direct outputs of the flip-flops 46 and 47 form the outputs 52 and 53 respectively, the inverse outputs of the flip-flops 47 and 48 form the outputs 54 and 55, respectively, and the input S of the flip-flop 46 forms the setting input 56 of the shift register 45. In addition, the linking block contains elements 57 and 58, the outputs of which are connected respectively to the outputs 23 and 59 of the anchor block, the first

45 inputs - respectively with outputs 52 and 53, second inputs - respectively with outputs 54 and 55 of shift register 45, third inputs - with input 22 of the binding unit and clock input

 49 of the shift register 45, the shift input 51 of which is connected to the input 20 of the anchor block, and the bus O connected to the installation input 56 of the shift register 45.

55 The control unit 11 (Fig. 3) contains an anchor block 19-1, 1 K.-flip-flop 61, frequency meters 62-1 and 62-2, tires O 63 and 1 64, and the shift-off.

the first register 45-1, the setup input 56 of which is connected to the input 24 of the control unit, the shift input 31 - with the bus O 63, the clock input 49 - with the output 23 of the block 19-1 and the output from the trigger 61, the inputs I and K which are connected to bus 1 64, direct and inverse outputs — with the first inputs 63 of the frequency meter 62-1 and 62-2, respectively, the second inputs 66 of which are connected to the input 23 of the control unit and the input 22 of the anchor unit 19-1, the input 20 of which is connected to input 26 of the control unit, as well as elements AND 67 and 68, element OR 69, RS-trigger 70, elements AND-NOT 71 and 72, the first inputs of which are connected No, respectively, with outputs 32 and 53, the second inputs - respectively with outputs 34 and 33 of the shift register 43-1, outputs, respectively, with the first and second inputs of elements And and 68, the third inputs of which are connected to outputs 73 of frequency meters 62-1 and 62 -2, respectively, the outputs, respectively, with the first and second inputs of the OR 69, the output of which is connected to the installation input S, one, trigger 70, the installation input R to the zero of which is connected to the input of the AO, the output to the input 28 of the control unit.

Frequency meter 62 (Fig. 4) contains And 74 - 76 elements, Invartor 77, anchor block 19-2, a counter 78, the counting input of which is connected to the output of an And 74 element, the setup input - with an output 39 of the anchor block 19-2 The input 22 of which is connected to the input 66 of the frequency meter and the first input of the And 74 element, the second input of which is connected to the input 63 of the frequency meter and the input of the inverter 77, the output of which is connected to the input 20 of the anchor block 19-2, the output 23 of which is connected to the first the inputs of the elements And 73 and 76, as well as a digital comparator (type 333 SP1) 79, a memory device The device 80 and the element OR 81, the output of which is connected to the output 73 of the frequency meter, the first input — with the overflow output of the counter 78, the second and third outputs — with the outputs of the AND elements 73 and 76, respectively, the second inputs of which are connected respectively to the outputs and

In digital comparator 79, the first input A of which is connected to the output of the counter 78, the second input B with the output of the storage device 80.

The device works as follows. After powering up the bus, resetting the 33 of each channel is logged. 1, which sets RS flip-flop 70 to the log state. O opens the diodes of isolation element 34 and raises the input voltage level of Schmitt triggers to the threshold for turning them on (Fig. 8). The triggers are disabled and a log appears on their outputs. 1, which is also maintained when the zero is cleared by the corresponding voltage dividers of 40 and 41 other channels. In this case, the blocking of the elements 13 and 14 is removed. The voltage dividers are calculated so that during the transition process associated with turning off the power in one of the channels, the corresponding Schmitt triggers of the other channels are turned off with such a voltage of the de-energized channel at which it sets generator 8 and logic elements function normally. I

Impulses of the master oscillator 8

the corresponding channel is fed to the counter 9, which together with the decoder 10 generates clock pulses with a frequency of fo / fti, where f is the frequency of the pulses of the master oscillator; m counter capacity. Elements 13 and 14, as well as element S1NI-NES 18 of one channel, through exchange inputs 29 and 30 and exchange input 21, form with a similar elements of other channels a three-stage trigger in such a way that, at the output of the element OR-NE, 18 one (master) channel will log 1, in the other two channels the log .O. In this case, elements AND 12 of the leading channel are opened, as well as one of the elements 15 and 16 of other channels and the same clock pulses pass to the output of the element OR 17 of each channel. The binding unit 19 forms the pulse of the installation of the counter 9 when a transition from the log occurs at its input 20. About in the log. 1. Since there are no such transitions in the steady state, the installation pulse is not formed and the phase correction of the counter 9 does not occur. The natural pulse count is not disturbed. The pulses of the high-frequency generator 6 are fed through the element 2I1 to the counter 2. The counting of the pulses begins. When counter 2 counts () pulses, where K is the capacity of the counter, the output of decoder 3 is a log. 1. The k-th pulse of counter 2 will overflow and at the output of the decoder 3, according to Wits log. Oh, che pulses - again log. Oh etc Thus, at the output of the decoder 3, pulses with a period of K / f are formed, where f is the frequency of the pulses of the high-frequency generator (plot 3 in Fig. 5). At the output of the delay element 4, delayed by 1 / pulses are formed (plot 4 in Fig. 5), which arrive at the first input and are gated through the second input of the ZI-NO element 5 by pulses of the high-frequency generator 6. The clock pulses arrive at the input of the one-vibrator 7. It forms from them pulses of duration, 5 / f (plot 7 in Fig. 5), which arrive at the third input of the ZI-HE5 element. To match the pulses at the inputs of this element, it is necessary to ensure the drift of the pulses of the delay element 4 relative to the clock pulses, i.e. perform inequality. 0 () which is a condition for frequency acquisition. It means that the phase shift of the pulses over one period of clock pulses must be greater than zero, but less than the period of the pulses of the high-frequency generator 6. Thus, the drift causes the reverse polarity of the high-frequency pulses to appear at the output of the ZI-HE5 element. Generator 6 (plot 5 in FIG. The duration of these pulses increases, and the duration of the pulses at the output of element I1 decreases, and a moment comes when counter 2 does not perceive the next pulse, i.e. a counting delay of 1 / f. In the next cycle, the pulses coincide at the inputs of the ZI element and there will be no natural counting of pulses. After some time, the drift will again bring the pulses together and the next correction of the phase of the counter 2 will occur, etc. Thus, a periodic the lengthening of all the pulses of the counter 2 by 1 / {, due to this the frequency of the pulses at the output of each channel of the device becomes a multiple of the clock pulse frequency. The accuracy of the coupling of the output pulses to the clock pulses does not exceed 1 / f, which means that the like signals Owls different channels not prevsh1aet this velichi.ny. The clock pulses of each channel are fed to the input 26 of the control unit 11 and to the anchor block 19-1, which links them to the high-frequency generator pulses 6, so that the output 23 of the anchor block 19-1 produces pulses of duration 0 5 / f, and the frequency of the frequency of the clock pulses. Equal frequency is ensured by periodically extending the period of these pulses by 1 / f, i.e. in the same way as in counter 2. Pulses of the anchor block 19-1 are sent to the clock input 49 of the shift register 45-1 and to the counting input C of the trigger 61, which operates in the frequency division mode by two. In the first half period, when the forward output of the trigger 61, there is a log. 1, element 74 of the frequency meter 62-1 opens and its counter 78 starts counting the pulses of the high-frequency generator 6. In the second half period, the counting of pulses begins at frequency meter 62-2, and at frequency meter 62-1 stops. In this case, in its counter 78, a code corresponding to the numbers K or K + 1 is written, which is fed to the first input A of the digital comparator 79, to the second input B which the frequency reference code is supplied from the memory 80. The lowest bit of counter 78 is not supplied to digital comparator 79, since its value varies over time and forms a counting error. Comparison of codes begins with the most significant bit. If the frequency lock condition is met, a log is generated at both outputs of the digital comparator 79. 0. After a log has been generated on the forward output of the flip-flop 61. The pulse counting has stopped, the anchor block 19-2 generates two non-overlapping pulses, the first of which polls the output state of the digital comparator 79, which resets the counter 78. In the next half-period, the counting of pulses in frequency meter 62-2 stops and starts again in frequency meter 62-1, etc. Thus, continuous monitoring of the frequency of the clock pulses of each channel is carried out (plots 6, 10, 19-1, 62-1, 62-2 in FIG. 6). I Suppose that in the master channel the frequency of clock pulses deviates by an amount at which condition (1) is not fulfilled. This deviation can be detected, for example, by the failure of the master oscillator 8, by the failure of the counter 9 (some kind of bit does not divide the frequency, but skips), the decoder 10 has the order (there are no clocks at the output, or they are doubled) or failure of the anchor block 19 (counter 9 is periodically set to the pulses), etc. If the frequency deviation of the clock pulses occurred as th / / - Y./ {O, then the frequency meters 62-1 and 62-2 count the number of pulses less than K. - K / f 1 / f then the meters (Frequencies count the number of pulses more Ki-1. In any case, polling digital comparator 79 will set Rs trigger 70 to log state 1 and the three-stage trigger switches. Any of the backup channels will become a source. If the clock deviates in the backup channels, their C5 triggers will trigger

70, but the tri-stable trigger does not switch. The presence of the log. 1 at the output of R5 flip-flop 70 indicates a channel failure, i.e. This device provides diagnostic status of the reserve. If the clock generation has stopped altogether (the frequency is zero), then one of the frequency meters will continuously count the pulses until its counter 78 overflows. In this case, setting the RS trigger 70 to the log state. 1 is produced by an overflow pulse through the OR element 81. Since the position of the master channel clock pulses at the first moment after switching of the three-stable trigger is randomly related to the correction of the phase of the master channel counter 9, the phase of searching for the clock pulses begins in all channels. At the same time, the non-phase of the same output pulses of different channels increases. The amount of non-sync depends both on the rate of divergence of the channels and on the search time for the phase of the clock pulses, which in turn depends on what number will be recorded in the counter 9 of the master channel. For the calculation of non-sync, consider the dual-channel mode of operation of the device, since the criterion of its performance is the in-phase operation of at least two channels at any possible seeding of 2 different channels to the same impulses of the counter, it may be that in one channel the impulse of the one-vibrator 7 is ahead, and in other channels it lags behind the impulse of the delay element 4, or vice versa in one channel behind, and in other channels ahead. In both cases, the in-phase operation of one channel with respect to the other channels is disrupted. To eliminate this, after switching of the three-stable trigger in the master channel at the output 23 of the anchor block 19, a pulse is formed that is bound to the pulses of the delay element 4; which corrects the phase of the counter 9, so that the next clock pulse takes up a unique phase position with respect to the pulses of the delay element 4 of each channel. Since during the correction of the phase of the counter 9, a change in the frequency of the clock pulses occurs, false frequency control and false switching of the three-stable trigger can occur. In order to eliminate this, the pulse of the anchoring unit 19 through the input 24 of the control unit 11 is written down log.1 to the first bit of the shift register 45-1, which is shifted by the clock pulses of the anchoring block 19-1. At the same time, negative-polarity pulses are generated at the outputs of the AND-NE 71 and 72 elements, which, by the second and third inputs of the E67 and 68 elements, block the outputs of the measuring frequency 62-1 and 62-2 for the time during which the frequency of the clock pulses is restored ( it takes 2-3 clocks). malfunction. Let the lead channel voltage be removed. Since Schmitt triggers 35 and 36 other channels are switched off at a voltage at which the leading channel is still stable in a transient mode, the common-mode operation of the channels at this moment is not disturbed. After the exchange links going from the de-energized channel and the working channels are blocked by the corresponding SchmiTt triggers, one of the two remaining channels will be the moderator. Take the worst case when the master channel counter 9 is set to such a state in which the search for the phase of the clock pulses occurs at maximum time (plots 6i, j, 4 |, j, in Fig. 7). In this case, the maximum nonsynchronization is 10,489 (K-0.5) “f (l -,) vri / f –K / j where O is the relative deviation of frequency f from the nominal; t - the value of non-phase is acceptable. Expressions (1) and (2) determine the functional relationship of the device parameters (., Fo f uS) at which it reliably functions in all possible types of failures. In order to enter a de-energized channel into operation, it is necessary to apply a supply voltage to it, as well. then in each channel to give the command reset. The invention makes it possible to ensure the in-phase operation of two channels in the event of any possible failure of the third channel, including when power supply voltage is removed, as well as monitoring the failure of channels.

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Claims (1)

A RESERVED DEVICE FOR SYNCHRONIZATION, containing in each of the three channels a serially connected master oscillator, a first counter and a first decoder, serially connected to the first AND element, a second counter, a second decoder, and also a delay element, a ZI-NOT element, a high-frequency generator and a one-shot, different the fact that, in order to increase reliability and controlability, a binding unit, a control unit, two voltage dividers, an isolation element, two Schmitt triggers, five AND elements are introduced into each channel , the zeroing bus, the OR-HE element and the OR element, the output of which is connected to the input of the one-shot, the first input - with the output of the second AND element, the second and third inputs - with the outputs of the third and fourth elements AND, the first inputs of which are connected respectively to the first and the second exchange inputs, the second inputs respectively with the third and fourth exchange inputs, as well as with the first inputs of the fifth and sixth AND elements respectively, the outputs of which are connected respectively to the first and second inputs of the OR-HE element, the third input of which It is connected to the output of the control unit, the output to the first input of the second AND element, the first exchange output and the first input of the binding unit, the second input of which is connected to the output of the delay element, the output with the installation input of the first counter and the first input of the control unit, the second input of which is connected with the output of the high-frequency generator, the third input - with the output of the first decoder, the second input of the second AND element and the second exchange output, the fourth input - with the zeroing bus and the output of the isolation element, the outputs of which are connected to respectively, with the fifth and sixth exchange inputs and inputs of the first and second Schmitt triggers, respectively, the outputs of which are connected to the second inputs of the fifth and sixth elements And, respectively, and the outputs of the first and second voltage dividers are connected respectively to the third and fourth exchange outputs, with the first and second the exchange outputs of the first channel are connected respectively with the third and first exchange inputs of the second, as well as with the fourth and second exchange inputs of the third channel, the third and even vertically, the exchange outputs are respectively with the fifth and sixth exchange inputs of the second and third channels, respectively, the exchange outputs of which are connected to the corresponding exchange inputs of the first and third, as well as the first and second channels, respectively. U ... 1195489