SU1173382A2 - Device for input of corrections into time storage - Google Patents

Abstract

1. DEVICE FOR INPUT OF AMENDMENTS TO THE TIME VARIABLE on azt of sv. No. 824118, characterized in that, in order to increase reliability, n + 1 AND-NOT elements, n + 1 control counters, n half-summers, second and third elements OR, third element AND, element NOT, trigger, driver and n + 1 buttons, with the outputs of all the elements AND-NOT connected to the clock inputs of the corresponding control counters, the outputs of all half-summers through the second element OR are connected to the first input of the third element AND, the first inputs of each of the first n elements AND-NOT are connected respectively to the outputs. And, the first the input of the last, (n + 1) -th element AND-NOT is connected to the output of the OR element, and the second inputs of each element AND-NOT are connected to the corresponding button, the outputs of the first n control counters are connected to the first input of the corresponding half-adder, and the output of the last (( The n + 1) control counter is NOT connected to the first input of the third element OR through the element, the second input of which is connected to the output of the third element. And, and the output from the D-input of the trigger, the C-input of which is connected to the first output of the imaging device, the R-input - to the input of the Device Installation, and the output to the output of the device is defective, the second input of the imaging device is connected to the generator output, the second output of the imaging device is connected with the R input of each of the n + 1 control counters, the second input of the third element I is connected to the input of the device lock, and the second inputs of the half adders - with the corresponding output (L of the ring shift register. 2. The device according to claim 1, characterized in that the driver contains sch This sensor is an NOT element, two AND elements and a frequency divider, the counting input of which is connected to the second input of the imaging device, the setup input - with the installation input of the counter .and the first input of the imaging device, and the output - with the counting input of the counter, the output of the first bit of which connected to the first inputs of two elements And, the output of the second bit is connected to the second input of the second element And through the element NOT to the second input of the first element And, and the output of the third bit to the third inputs of two elements And, the output of the first element And is connected to ne vym shaper output and the output of the second AND gate with the output of the second.

Description

one

The invention relates to a pulse technique and is intended for reliably counting and dividing the pulse frequency in the conditions of failures and failures of individual elements,

According to the main auth. № 824118 known device input corrections to the time keeper, containing i nerator, the output of which is connected to a multi-drop delay line, whose taps are connected to the first inputs of two-input elements K, the second inputs of which are connected to the outputs of the bits of the ring shift register, and the outputs through the OR element connected to the input of the time storage, two RS-flip-flops, the inputs of the first of which are connected to the tires of the signal of the sign of the amendment, and the outputs are connected to the first inputs of the two input gate elements And, the outputs of which are connected to the input m ring shift register, the second inputs of the three-input elements And connected to the output of the second RS-flip-flop, S-input of which is connected to the offset signal, and the R-input connected to the output of the counter, the delay element and an additional element OR, the input is connected to the outputs three-input elements And, and the output is connected to the input of the counter, and the third input of the first three-input element And directly, and the third input of the second three-input element And through a delay element connected to the input of the time storage.

With some failures of elements And it is possible to connect to the input of the time keeper of the withdrawal of the delay line adjacent to the correctly connected outlet. This fault leads to the fact that the subsequent input of the correction to the time keeper input begins to receive a pulse sequence of twice the frequency, and with a duty cycle equal to two, a constant potential. This leads to a complete failure of the time keeper. Undetected failures result in the time stamp being generated by the generated time stamps failing.

The purpose of the invention is to increase the reliability of the device,

FIG. shows a block diagram of the proposed device; in fig. 2 - timing charts 33822

you devices; figure 3 - timing charts, the work of the driver.

The device contains a generator 1, 5 delay line 2, for example, with three branches, a group of elements AND 3-5, element OR 6, time keeper 7, RS flip-flops 8 and 9, first and second elements AND 10 and 11, a ring register 12 shifts, an additional element OR 13, a counter 14, an additional delay line 15, four elements NAND 16-19, four counters 20-23 controls, three half C adders 24-26, a second element OR 27, a third element AND 28, an element NOT 29, the third element OR 30, the trigger 31, the driver 32 and the four buttons 33-36. Element Outputs

Q AND-NOT 16-19 are connected to the clock inputs of the corresponding counters 20-23, and the outputs of half-adders 2426 through the element OR 27 are connected to the first input of the element AND 28. You, the generator 1 is connected to the input of the delay line 2, the taps of which are connected to the first the input elements And 3-5, the second inputs of which are connected to the outputs, respectively, And,

8, From the ring register 12 shift, and the outputs through the element OR 6 with the input of the time keeper 7. The first inputs of the elements 10 and 11 are connected respectively to the direct and inverse output of the RS flip-flop 8,

5 inputs S and R of which are connected to

inputs 37 and 38 for inputting the sign of the correction, respectively, the second inputs of the elements. AND 10 and 11 are connected to the direct output of the trigger 9, and outputs 0 to the control inputs of the shift register 12 and through the OR element 13 and the counter 14 to the R input of the RS flip-flop

9, the S-input of which is connected to the input 39 of the amendment. The output of the terminal OR 6 through the delay line 15 is connected to the third input of the element AND 0 and directly to the third input of the element 11. The first inputs of the elements AND-NOT 16-18 are connected

0, respectively, with the outputs of elements AND 3-5 of the group, the first input of the element AND-NOT 19 is connected to the output of the element OR 6, and the second inputs of each element AND-NOT 16-19 are connected

5 with the corresponding button 33-36.

The outputs of the counters 20-22 are connected respectively with the first inputs of half-adders 24-26, and the output of the counter

3II

23 through the element 29 is connected to the first input of the element SHSh 30, the second input of which is connected to the output of the element 28 and the output to the input of the trigger 31. The input of the trigger 31 is connected to the first output of the imager 32, the R input to the input 40 Installing the device and with the first input of the imager 32, and the output - with output 41 The device is defective. The second input of the imaging unit 32 is connected to the output of the generator 1, the second output of the imaging unit 32 is connected to the R-input of each counter 2023, the second input of the And 28 element is connected to the input 42 Device lock, and the second inputs of the half-accumulators 24-26 - to the outputs A, B, C annular shift register, respectively.

The imaging unit 32 consists of a frequency divider 43, a counter 44, a HE 45 element, and And 46 and 47 elements. The counting input of the divider 43 is connected to the second input of the imaging unit 32, the setup input of the divider 43 is connected to the installation input of the counter 44 and to the first input of the imager 32, and the output of the divider 43 is connected to the counting input of the counter 44, the output of the first bit of which is connected to the first inputs of the And 46 and 47 elements, the output of the second bit is connected to the second input of the And 47 element and through the inverter 45 to the second input of the And 46 element, and the output third bit yes third the inputs of the elements And 46 and 47, the Output of the element And 46 is connected to the first input of the imaging unit 32, and the output of the element And 47 - with the second output of the imaging unit 32.

The introduction of additional elements and connections allows monitoring the taps of the delay line to the input of the time store using the control counters and half adders to continuously determine the state of health of the correction input device or its Fault resulting in a malfunction of the time store.

Increased reliability is ensured due to the possibility of timely detection of malfunctioning of the inputted communication elements by monitoring their repair without storing the work, store the timer by introducing elements with buttons. Opportunity

3382 4

Such a check allows to achieve high reliability of the time keepers even with long-term continuous operation.

The device operates as follows.

After switching on the device (Fig. 1) to input 40 of the installation, an i-pulse is applied, which sets the trigger 31 10 to state O. The same pulse sets the zero position to divider 43 and counter 44 of mapper 32. Preliminary consider the mode without entering the correction. When e is IT at input 42 Blocking is logical 1, From the output of the generator I to the input of the delay line 2 (Fig. 2a) a pulse sequence of the reference frequency arrives. 0 At the outputs of the ring shift register 12 there is a unitary code, for example, containing a single logical 1 at its output B (Fig. 26), at the remaining outputs

5 of the ring register 1.2 shift while O (Fig. 2c). The pulses (in this example, from the second branch of the delay line 2) through the open element AND 4 and the element OR 6 arrive at the input of the time-keeping device 7. Buttons 33-36 are disabled, and therefore the logical inputs I, the pulses from the output of the AND 4 element through the open element AND-NOT 17, go to the second inputs of the zlementots AND-NOT 16-19,

5 ac output of the item ШШ 6 through

an open element AND-NOT 19, respectively, arrive at the C-inputs of counters 21 and 24 with a conversion factor k. Conversion factor k

0 counters 20-23 selected in such a way as to ensure the smooth operation of the logic elements included at the output of these counters. On the R-inputs of counters 20-23 with

5, the second output of the imaging unit 32 (output of the element 47) receives reset pulses (Fig. 2d), which are formed as follows. Pulse sequence

0 with a period T is fed to the input of a frequency divider 43 with a division factor t, from the output of which the pulse sequence is periodically fed to the input of the count-.

5 chika (Fig. For). At the output of the first, second, third bits of the counter 44, pulse sequences are formed (FIG. 3B, c, d, respectively). The reset pulses are formed at the output of the AND 47 element (FIG. RE) so that the current pulse corresponds to the 111 state of the counter - 44. The division factor m of the frequency divider 43 is chosen so that the period of the following pulses from the output of the AND 47 elements is equal to the counting period of the counters 20-23, Since the conversion factor of the counter 44 is 8, as follows from the comparison of FIG. For and FIG. Zg, then k in. At the output of that of the counters 2022, to the input of which a pulse sequence arrives (in this case, this counter 21), as well as the output of the counter 23 simultaneously, pulses are generated (respectively Fig. 2e, g), and at the output of the remaining counters 20-22 (in this case, the counters 20 and 22) remain with the logic level O (fig.2e) At the output of the element 48 of the imaging unit 32, control tact pulses are generated (fig, Ze) corresponding to state 10 of the counter 44. Therefore, these pulses are ahead of the reset pulses from the output of the element And 47 formers 32, and the edges of each control pulse coincide in time with logical 1 at the output of counters 20-22, in this case, counters 21-23 (Fig. 2h). At the time of the fronts of these Pulses, the code combination on the first inputs of half-adders 2426 coincides with the code combination at the outputs of shift registers 12, and at the output of each half-adder there is a logical O. The level of logical 0 from the output of each half-adder 24-26 through the OR element 27 and the open element AND 28 enters the second input of the OR element 30, the first input of which enters, also level logical O is inverted by the inverter 29 logical 1 from the output of counter 23. Thus, at the moment coinciding with the front of each pulse of the control cycle from the output of the former 32, the D input of trigger 31 has a logic level O, the trigger 31 remains in zero state and output 4 {{faulty device, there is no fault signal. In the proposed device, a failure resulting in a change or disappearance of the impulse sequence at the input of the time saver 7 when there is no correction input is detected as follows. The loss of the pulse sequence at the input of the time keeper leads to the fact that the pulse 23 sequence does not arrive at the input of the counter 23 through the IS-NOT element 19, the counter 23 remains in the state O, therefore through the inverter 29 and the element OR 30 the constant input Logical 1. When the trigger edge 31 of the control pulse pulse arrives at the C input from the second output of the driver 32, the trigger 31 overturns at 1. Output 41 The defective device is affected by a constant p-potential I - a fault signal. Failures not detected by counter 23 are detected by counters 20-22. Suppose, as a result of a failure, an improper connection of a tap occurred, for example, the first. Such a failure is not detected by counter 23. But at the same time, impulses arrive through the element AND-HE 18 to the input of the counter 22, and a positive impulse is formed at its output. Due to the fact that at the output of the ring register 12. Shift, there is a logical 0, a positive: pulse from the output of counter 22 passes through half-adder 26, and then through the elements OR 27, AND 28 and OR 30 to the input of the trigger 31, Thus, the moment coinciding with the front of the pulse of control from the output of the imaging unit 32, at the input of the trigger 31 there is a logic level 1 and the trigger 3 tilts to 1. Output 41 A permanent potential 1 is formed at the fault of the device - a fault signal. In this way, any, including multiple, malfunction is detected, which leads to the implication or disappearance of the pulse sequence at the input of the time saver 7 in the operation mode with no correction input. Indeed, counters 20-22

7n

and half-accumulators 24-26 control the connected taps of the delay line 2 by monitoring all the outputs of elements AND 3-5 of the group, and the counter 23 with inverter 29 provides control of the output of the element OR 6 connected to the input of the time storage 7.

Directly. Before entering each discrete correction to input 42, a lock is given a logical value. When a correction is entered, a change in the code pattern occurs at the outputs of the ring 12 shift register. Suppose, for example, that one increment correction is introduced in the lateral direction. There is a change in the code combination 010 (respectively, at the outputs A, B, C of the ring register 12 shift) to the code combination 100 (FIG. 26, c). Element And 4 is closed at the second input, and Element 3 at the second input opens. The second tap of the delay line 2 is disconnected from the time store 7 input, and the third tap is connected.

Due to the presence of the logic level O at the input 42, the blocking element AND 28 is closed during the connection of the taps, therefore it is unnecessary to synchronize the operation of the counters 20-22 and the moment of switching the taps of the delay line 2, since in the case of forming the logic level 1 at the output of any of the I-half-matators at the moment of switching, this signal does not pass to the B input of the trigger 31.

Despite this interlock, the control does not stop due to the presence of a control circuit consisting of an AND-HE element 19, a counter 23, an inverter 29 and an OR element 30.

After a period of time known enough to end the transients in the device when switching the taps of the line 2 delay8

ki, stopping the supply of logic level O to input 42 Blocking. Failure troubleshooting

5, at the entrance of the time custodian 7, is carried out by periodically monitoring the work of the slinger 7 without any action as follows.

After entering a discrete correction

0 operator presses a button from among the buttons 33-35, corresponding to the control circuit of the connected outlet. In this case, the operator presses the button 33. This closes the element

5 AND-NO 16, the pulse 20 stops receiving a pulse sequence from the output of the element 3, the output of the counter 20 remains at a constant level of logic O, to

0, the output of half-adder 24 is formed by logical 1, which causes f to overturn trigger 31 into 1, and the output 4I malfunctions a fault signal. Serving

5 pulses at input 40 Setting the trigger returns to its original state. Thus, with each entered digit, the next circuit from the number of circuits is monitored.

The controls containing the elements INE 16-18, the counter 20-22, the half-adders 24-26, the elements OR 27, AND 28, OR 30 and the trigger 3 without distortion. the pulse sequence at the input of the time keeper 7.

The control circuit, containing the element IS-NE 19, counter 23, inverter 29, element SHVD 30 and trigger 31, is also monitored without distorting the signal at the input of the time storage 7 by pressing button 36, the closing element IS-NOT 19. In contrast to the previously discussed control circuits, the control of this circuit can

performed regardless of the number of the connected delay line 2 delay.

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Claims (2)

1. DEVICE FOR INTRODUCING AMENDMENTS TO THE TIME KEEPER by ed. St., No. 824118, characterized in that, in order to increase reliability, n + 1 NAND elements, n + 1 control counters, n half adders, second and third elements are introduced into the device OR, third AND element, NOT element, trigger, driver, and n + 1 buttons, the outputs of all AND elements NOT connected to the clock inputs of the corresponding control counters, the outputs of all half adders through the second OR element connected to the first input of the third AND element, the first inputs each of the first n elements AND NOT connect respectively, with the outputs of the AND elements, the first input of the last, (n + 1) th AND-NOT element is connected to the output of the OR element, and the second inputs of each AND-NOT element are connected to the corresponding button, the outputs of the first η control counters are connected to the first the input of the corresponding half-adder, and the output of the last (n + 1) -th control counter through the element is NOT connected to the first input of the third OR element, the second input of which is connected to the output of the third element. And, and the output is with the trigger D-input, the C-input of which is connected to the first output of the driver, the B-input is with the device installation input, and the output is with the output. The device is faulty, the second driver input is connected to the generator output, the second driver output is connected to By the B-input of each of the n + D control counters, the second input of the third AND element is connected to the Blocking input of the device, and the second inputs of the half adders are connected to the corresponding outputs of the circular shift register. 2. The device according to π. 1, characterized in that the shaper contains a counter, an element NOT, two AND elements, and a frequency divider, the counting input of which is connected to the second input of the shaper, the installation input - with the installation input of the counter .and the first input of the shaper, and the output - with the counting, the counter input, the output of the first discharge of which is connected to the first inputs of two AND elements, the output of the second discharge is connected to the second input of the second AND element and through the element NOT to the second input of the first AND element, and the output of the third discharge - with the third inputs of two elements And, the output of the first element And is connected to the first output of the shaper, and the output of the second element And with the second output of the shaper. SU. ₍ . „JLLZ33S2