SU1034196A1 - Redundancy scaling device - Google Patents

Description

The invention relates to automation and computing technology and can be applied in redundant devices for performing pulse counting on any basis. A redundant frequency divider is known, which contains in each channel a pulse counter on EC triggers, a comparison circuit and a majority element 1. This device has drawbacks. The first disadvantage is that the known device is not operable in single channel mode. For example, if out of order. - in two channels) elements located up to majority blocks (for example, output triggers of counters, this unambiguously leads to blocking of all major elements and, as a result, to complete dissynchronization of the counters and their stopping. a major element of at least one channel (its inputs lead to the failure of the redundant system as a whole. For example, if a majority element in the first channel is broken and its inputs pass plus the supply voltage, then this means that All interchannel links (with trunk structure) are in the state of logical terminal. Similarly, if a short circuit occurs on the negative power supply bus inside the majority element, then the entire exchange highway is in the state of logical zero. Therefore, if the failure occurred at least in one channel, then it entails the failure of all three channels. A redundant recalculation device is known to contain three channels, each of which contains an input bus, a majority element, and tchik, DK-trigger, two elements are NOT and the element IS-NOT, the output of which is connected to the input E for the first time row of the counter and connected through the first element to the input 15 of the OK-terminal, the clock input of which is connected to the input bus and the clock input of the counter corresponding to the discharge outputs of which are connected to the inputs of the I-HB element, the installation inputs to the zero of all bits, except the first, are connected to the input of the second element NOT, the output of which is connected to the input K of the first discharge of the counter, the output of the main element is connected to the input of the second element is NOT and with the input of 1C. EK-trigger, the inputs of the majority element are connected to the outputs of the EK triggers of all channels 2. The known device has the following disadvantages. The failure of an EC trigger in two channels so that the outputs of the triggers are constantly present, for example, a high level, leads to the fact that majority elements are blocked in all channels, and this in turn leads to a failure of the redundant system as a whole. Therefore, the known device cannot operate in single channel mode. The withdrawal of the majority element at least in one channel {by its inputs; leads to the release of the redundant system as a whole. For example, if the inputs of the majority element in the first channel are shorted to the positive power bus, then the entire exchange highway is in a state of logical one. Likewise, if a short circuit to the negative power bus occurs inside the majority element, then the entire exchange highway is in the logical zero state. The failure of only one element, which is also the main element of the scaling circuit (and only the exchange element /, results in a failure of the redundant system as a whole. The purpose of the invention is to increase the reliability of operation. To achieve this goal in a reserved scaling device, three channels, each of which contains an incoming bus, a counter, the first EC tripler, two NOT elements and an AND-NOT element whose output is connected to the input E of the first discharge of the counter and NOT connected to the input through the first element о К trigger, clock input of which is connected to U by input bus and clock input of counter, corresponding outputs of bits of which are connected to inputs of NAND element, installation inputs to zero of all bits, except the first one, are connected to input of second element NO, output which is connected to the input K of the first counter of the counter, the second JK.trigger, two elements AND and the OR element, whose output is connected to the input of the second element NOT, the clock input and output D of the second IR trigger, are connected to each channel, and input 3 ne first G7K - trigger, the outputs of the first and BTopot-o .TU -triggers are connected respectively to the first inputs of the first and second elements AND, the outputs of which are connected respectively to the inputs K of the first and second EC of the triggers and the second inputs of the first and second elements And the first channel is connected respectively to the outputs of the first EC triggers of the second and third channels, the second inputs of the first and second elements of the second channel are connected respectively with the output of the first DK trigger of the first channel and the output of the second channel a third channel 5K latch, the second inputs of the first and second members and the third channel are connected respectively to the outputs of the second

DK triggers of the first and second channels.

FIG. 1 is an electrical diagram of a single channel of a redundant scaler in FIG. 2 - potential diagrams of device operation.

FIG. 1 denotes an input bus 1 / elements NOT 2 and 3, a counter 4, an element AND-NOT 5, 7K triggers 6 .and 7, an output bus 8, an input bus 9,, an output 10, an input bus 11, And elements li and 13 and the element OR 14

The input bus 1 is connected to the clock inputs of the counter 4 and 17K trigger B and 7, which inputs are connected respectively to the output tires 8 and 10 and. The first inputs of the elements are And 12 and 13, the second inputs of which are connected respectively to the input buses 9 and 11, the outputs of the elements 12 and 13 are connected respectively to the inputs of the element OR 14, the output of which is connected to the inputs of the installation to zero all bits, except the first counter 4 and connected through the element NOT .2 to the input K of the first discharge of the counter: ik 4, the input E of the first discharge of which is connected to the input of the element AND-NOT 5 and to the input of the element NO 3, the output of which is connected to the inputs of the DK flip-flops 6 and 7. The corresponding outputs of counter bits 4 (in this case, the inv The main output of the first discharge and the direct outputs of the remaining bits are connected to the inputs of the element - NAND 5.

The input buses 9 and 11 of the first channel are connected respectively to the output tires 8 of the second and third channels, the input buses 9 and 11 of the second channel are connected respectively to the output tires 8 and 10 of the first and third channels, the input buses 9 and 11 of the third channel are connected respectively to the output tires 10 first and second KjaHanoB.

FIG. 2 shows potential diagrams of 15–24 signals, respectively, on input bus 1, at the outputs of the first, second, third, and fourth bits of counter 4, at the output of the element. AND – NO 5 and at tires 8–11.

. The device has a conversion factor, K-15. In the initial state, all bits of the counter 4 are in the zero state, 3K-triggers

 7 also reset. At the entrance to the first discharge of the counter, there is 1 HIGH potential, creating conditions (together with a high level at the input 3) for the operation of the first discharge of counter 4 in the counting mode.

The operation of the device (Fig. 1) begins with the delivery of counting pulses through bus 1. The process of filling the counter takes place. After the counter counts the fourteenth impulse, a high potential appears at the output of the HE 3 element. It arrives at the J-inputs of the flip-flops 6 and 7. On the falling edge of the next (fifteenth) input hulse, the flip-flops 6 and 7 are set to one. levels from tires B and 10 to exchange into other channels. Counter 4 on the trailing edge of the fifteenth pulse passes to the next (zero state.

If the channels work in phase, then output buses 9 and 11 (simultaneously and in phase with signals, on output buses 8 and 10) receive confirmation signals in the form of high levels. At the outputs of the And 12 and AZ elements, high levels appear that feed into the K-inputs of the flip-flops b and 7 and pass through the OR 14 without inverting. A high level from the output of the element OR 14 comes to: the R inputs of the installation to zero bits of the counter 4 and sets the most significant bits of the latter to the zero state. Simultaneously with the installation of zero in one hundred M11 of the bits of the counter at the input K of its first discharge, the zero level appears.

On the falling edge of the next. (First) pulse arriving on. bus 1, the first counter of the counter is switched to the single state, and triggers 6 and 7 go to zero, removing the caNDtJM exchange signals from bus b and 10. Then the process repeats. The process of the next filling of the counter occurs. The described operation of the device during in-phase channel operation is explained by potential diagrams 15-24 (Fig. 2).

Consider the case when the channels for any of the random reasons were out of phase,. Counters 4 in the channels are in different positions and have one shift relative to the other.

Let, for example, in the first channel, on the trailing edge of the fifteenth pulse, triggers b and 7 are introduced into one state. At the same time, high levels appeared on tires 8 and 10, which were fed to the second and third channels, respectively. Let the counter of the second channel lag behind the first one, for example, by four periods of counting pulses, and from the second channel by eight periods. After four periods of counting pulses in the second channel (tripping edge of the fifteenth pulse is triggered by triggers b and 7. A high level is supplied from buses 8 and 10 of the second channel to buses 9 and 11 of the first and third channels, respectively, in the first and second Channels are processed by elements AND 12, which spread a high level from their outputs through element OR 14 to the installation inputs R of the higher bits of the counters 4. At this moment, the higher bits of the 4IIKOB are in the same zero state. at the inputs of the first bits of the counters of the first and second channels are set to zero, so on the falling edge of the 6 counting counting pulse 1-pulse, the first bits of the count 4 are in the same unit state, and the triggers in these channels are reset to zero state. The process of mutual synchronization of the first and second channels occurs. Now these channels work in phase. However, the triggers 7 of the first and second channels are in the single state (in the waiting state /. .A further four periods of counting pulses in the rubbed channel (on the falling edge of the fifteenth pulse, triggers 6 and 7 are set to one state. A high level is supplied from buses 8 and 10 to tires 11 of the first and second channels, as well as to the first inputs of the elements And 12 and 13 of their (third) channel. In the first .. and second channels, elements 13 and 13 are triggered, and in the third channel - elements 12 and 13 simultaneously. Next, the mutual synchronization process described for the first and second channels occurs. Counters sun The ex channels work in phase, and the triggers 6 and 7 are reset to the zero state before the next time of mutual synchronization (once per counter count cycle. The described process The operation of the device assumes the phase arrival of the counting pulses in all channels. The proposed device is more reliable than the known ones. For example, if Since the second and third channels and they constantly send high levels to the tires 9 and 11 of the first channel, this does not affect. its operability, which is explained by the fact that, in order for the And 12 and 13 / elements to work, it is necessary that the triggers b and 7 of the first channel are in a single state. But in this state they are in strict correspondence (diagrams 21-24 in Fig. 2 /. The rest of the time triggers 6 and 7 are in zero state, but if the second and third channels send permanent zeros to the exchange, then Elements 12 and 13 are not affected. On the basis of the pronounced description, the proposed device can operate in single-channel mode, i.e. in the presence of faults in two channels. Now consider the situation when, for example, the element 12 of the second channel went out of order so that its inputs were shorted to the power supply bus. A low level goes to the "pins 8 and 9 of the first channel, but it cannot interfere with its operation. All three channels will work in phase because the second channel has good communication with the third channel, and the third channel is in turn connected with the first one. If in the second channel the same malfunction has an E 13 element (its inputs are also shorted to the minus power bus), then it turns out that the second channel will operate independently and it will not be in sync with the first and third. The latter will work in phase, due to the fact that there is a good connection between them. The problem of the in-phase operation of the reservation channels of recalculation of one's schemes is extremely important in connection with the need in computer systems to exchange information for the elimination of single failures. If there is an I 12 in any channel (for example, in the torus / VB of the T1 element from the torus (or E13 element so that its inputs are shorted with the positive power bus, then a high level from its tires 8 and 9 extends to buses B and 9 the first channel blocking its operation. However, in this case, which is most difficult for the proposed device, the third reservation channel will remain operational. Thus, the proposed device is more protected from the effects of the indicated disadvantages than the known ones. The ring is more reliable than the main circuit. For example, a break in the links between the first and third channels (the ring can be broken in any other place) does not affect the performance of the redundant device at all. Breaking the ring in two places leads to the isolation of

any channel, but the other two channels are connected to each other and working), therefore, it is synphaeo.

Due to the fact that the proposed device allows to increase the reliability of the device.

in which it will be used, it is possible to reduce the multiplicity of block reservations, as well as to obtain an economic effect. effect due to reduced backup ratio

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Claims (1)

a redundant TRANSMISSION DEVICE containing three channels, each of which contains an input bus, a counter, a first trigger, two NOT elements and an NAND element, the output of which is connected to input 3 of the first digit of the counter and through the first element NOT to the input J of the first ZKtrigger, the clock input of which soy * g · is din with the input bus and the clock input of the counter, the corresponding output of the bits of which are connected to the inputs of the AND-NOT element, the installation input to zero of all bits except the first, connected to the input of the second element NOT, the output of which from is single with the input, K of the first category of the counter, characterized in that, in order to increase the reliability of operation, the following are introduced into each channel: a second 9K trigger, two AND elements and an OR element, the output of which is connected to the input of the second element NOT, a clock input and input 3 of the second ZK trigger are connected respectively to the clock input and input "! 7 of the first ZK-trigger, the output of the first and second ZK-triggers are connected respectively. respectively, with the first inputs of the first and second elements AND, the outputs of which are connected respectively to the inputs K of the first and second SC-triggers and connected to the inputs of the OR element, the second inputs of the first and second elements AND of the first channel are connected g respectively with. the outputs of the first 1 ZKx-triggers of the second and third £ channels, the second inputs of the first and second Z second elements AND of the second channel are connected with C respectively with the output of the first ZK-trigger of the first channel and 'S with the output of the second ZK-trigger of the third * ** go channel , the second inputs of the first and second elements of the third channel are connected, respectively, with the outputs of the second 'EC-triggers of the first and second channels. with