SU1562898A1 - Multichannel device for information input/output - Google Patents

Abstract

The invention relates to computing, in particular, to software control of process equipment. The purpose of the invention is to increase reliability. The device contains blocks 3 and 4 galvanic isolation, indicator 6, elements AND 2, 11, 12, fuse 5, majority element 13, element AND-HE 9, delay element 10, block 8 addition modulo two, trigger 7. The invention allows to increase the reliability of the device by simplifying it and protecting against short circuits of the load. 2 Il.

Description

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The invention relates to computing, in particular, to software control of process equipment, and can be used in programmable controllers.

The purpose of the invention is to increase the reliability of the device.

FIG. 1 shows a functional diagram of the device; figure 2 - the timing diagram of his work.

The device (Fig. 1) contains channels 1 according to the number of bits of the information input and in each channel 1 the first element I 2, the first 3 and the second A blocks of galvanic isolation, fuse 5 and indicator 6, the output of the first block 3 galvanically isolated through fuse 5 is connected to the input-output of channel 1, which is connected via an indicator 6 to the input of the second galvanic isolation unit 4, the output of the co-trigger 7, the output of which is connected by the error output of the device.

The device works the following about

 at once.

The device allows to use any input-output channel 1 or as an external input device, a lo bo output. If the input-output channel 1

d is used as input then

between it and the positive potential of the DC network, the automation elements are connected (for example, to final switches, buttons are adjusted

15 sensors, etc.). If the input-output channel 1 is used as an output, then automation elements (for example, relay coils, electromagnets, etc., are connected between them and the negative

20 potential of a network of constant voltage.

Initially due to the installation on the bits of the information input of a device of logical O signals

thirty

It is connected to the first input of the first 25 and supplying the signal of logical 1 to the element I 2 and the corresponding output of the device. In addition, the device contains a trigger 7, block 8 addition modulo two, the element AND-HE 9, the delay element 10 and in each channel. The second 11 and third 12 And elements and the majority element 13, the output of which is connected to the input of the first block 3 galvanic the second input of the first element AND 2 of its channel 1 and the corresponding discharge of the group of inputs of block 8 addition modulo two, the output of which is connected to the information input tpnrrepa 7 and the first input of the element Q AND-NOT 9, the output of which is connected to the first inputs of the third elements And 12 each to The channel, the output of the first element and 2 channels is connected to the first input of the major element 13 of its channel and the corresponding bit of the second group of inputs of the adding unit 8 modulo two5 each bit of the information input is connected to the second inputs of the second P and the third 12 elements And its own channel 1, the outputs of which are connected to the second and third inputs of the majority element 13, the synchronous input device is connected to the first input of the second 1 and the third input of the third 12 elements AND of each channel 1 and the input of the delay element 10, the output of which is inen with the second input element AND-NOT 9 and sync

45

50

55

the synchronous input of the device is zeroed by the outputs of the majority elements 13 in channels 1. The output state of the majority element 13, corresponding to the input state of the external input-output channel 1, must be maintained at the level corresponding to the logic 1, therefore the phototransistor of the galvanically isolated unit 3 corresponding to the input is disabled. In this mode of channel operation, the chain of fixations is erroneous. ki is blocked by element 2 for signaling the logical O signal from the output of the majority element 13. At the same time, from the specified channel, the inputs of block 8 receive the same logical O signal. This prevents the formation of an error signal at the output of block 8 at any input signal value - the output of the channel arriving - through the block 4 galvanic isolation of the device output.

In the mode of using the output channel during its normal operation, the signals at the output of the AND 2 element and the primary element 13 are always the same. Therefore, block 8 of modulation two does not generate error signals. At the output of the latter, short-term interference signals may occur when the state of the kan changes due to transients in the device node. However, these signals are not perceived by gating.

trigger 7, the output of which is connected to the error output of the device.

The device works as follows.

The device allows you to use any input-output channel 1 or as an external input device, or output. If the input-output channel 1

used as input then

between it and the positive potential of the DC network, they connect automation elements (for example, limit switches, control buttons,

5 sensors, etc.). If the input-output channel 1 is used as an output, then automation elements (for example, relay coils, electromagnets, etc.) are connected between them and the negative potential of the DC voltage network.

Initially due to the installation on the bits of the information input of a device of logical O signals

0

5 and signaling a logical 1 to Q

five

0

55

the synchronous input of the device zeroes the outputs of the majority elements 13 in channels 1. The output state of the majority element 13 corresponding to the input state of the external input-output channel 1 must be maintained at a level corresponding to logical 1, therefore the phototransistor of the galvanically isolated unit 3 corresponding to the input disabled. In this channel operation mode, the chain of fixations is erroneous. ki is blocked by an And 2 element by supplying a logical O signal from the output of the majority element 13. At the same time, from the specified channel, the inputs of block 8 receive the same signals of logical O. This prevents the formation of an error signal at the output of block 8 at any input signal value the output of the channel, which arrives, through the galvanic isolation unit 4 to the output of the device.

In the mode of using the channel as an output during its normal operation, the signals at the output of the AND 2 element and the majority element 13 are always the same. Therefore, modulo two addition unit 8 does not generate an error signal. At the output of the latter, short-term interference signals may appear when the channel state changes due to transients in the device nodes. However, these signals are not perceived by gating.

element AND-NOT 9 and trigger 7, delayed by the transient time level of the signal applied to the synchronous input of the device. The delay is provided by a delay element 10, while the latter passes the zero level from its input without delay.

In the event of a fault in the event of a short circuit in the load or a blown fuse 5 due to the appearance at two inputs of the majority element 13 of the logical O signals, the latter is switched off. Thus, the output transistor of the galvanic isolation unit 3 does not have time to go out of service. When an attempt is made to turn on the defective channel, the out-of-phase signals appear at the outputs of the majority element 13 and element 2.

After the delay element 10 is triggered (Fig. 2), a trigger 7 is set on the leading edge of the error signal from the output of block 8, energizing the error output of the device, and the major element 13 by the signal from the output of the NAND 9 element - to state O. The output transistor Unit 3 galvanic isolation also does not have time to get out of order, as the duration of the delay element 10 is quite small. After the fault is eliminated and the next entry into the device is initialized, the trigger 7 is reset.

Claims (1)

Invention Formula A multichannel device for input-output information, containing in each channel the first element I, the first and second blocks of galvanic isolation, fuse, indicator, output of the first block galvanic 0 0 through the fuse is connected to the indicator input and is the input-output of the device, the indicator output is connected to the input of the second galvanic separation unit, the output of which is connected to the first input of the first element I and is the corresponding output of the device, characterized in that in order to improve the reliability of the device, a trigger is added to it, a modulo-two addition unit, an AND-NOT element, a delay element and each channel has a second and third AND elements, a major element, the output of which is connected to the input the house of the first galvanic isolation unit, the second input of the first element AND of this channel and the corresponding input of the first group of the modulo-two unit, the output of which is connected to the trigger information input and the first input of the NAND element whose output is connected to the first inputs the third elements AND each channel, the output of the first | An element of the channel is connected to the first input of the major element of this s channel and the corresponding input of the second group of the modulo-two modulo unit; the second inputs of the second and third (And elements are combined and are the corresponding information input of the device; the outputs of the second and third elements are connected to the second and the third input of the majority element, the input of the delay element is connected to the first inputs of the second and third inputs of the third And elements, and is the synchronous input of the device, the output of the delay element is connected to the second input of the NAND element and the synchronous input of the trigger, the output of which is the output of the device error. five 0 five 0 ZJtVJfloc cmpoS at with jj Jv FIG 2