SU841099A1 - Pulse synchronizing device - Google Patents

Description

54) DEVICE FOR SYNCHRONIZATION OF PULSES

one

The invention relates to a pulse technique and is intended to synchronize asynchronous pulses with clock pulses. ,

A device for synchronizing asynchronous pulse sequences with clock pulses, performed on microelectronic circuits using trigger cells, and containing an input trigger, an output, a trigger, three AND elements and two HE1 elements, is known.

 However, when developing digital devices on microelectronic circuits, the reliability of their operation is determined not only by the probability of failure of the integrated circuit, depending on the circuitry characteristics of the circuit itself, but also by the probability of false switching (failure) of the trigger circuits under the influence of external interference. The reliability of a triggered circuit, in turn, depends on the degree of mutual electromagnetic influence of external intercircuit connections, resulting from crosstalk and, ultimately, on the technical implementation of the wiring connections. The relatively high sensitivity of the ho trigger, the ability not only to transmit, but also capture the effects of interference and turn it into false information, makes the trigger more susceptible to interference in digital

devices. Therefore, when exposed to external interference, especially in the onboard equipment, the likelihood of triggers included in devices increases, which can lead to false output information.

The closest in technical essence to the present invention is a synchronization device comprising the first and second TaKTHpyeNwe triggers, the RS flip-flop, the first and second two-input elements AND-NOT, the bus of the first clock pulse, the bus of the second clock pulse, the bus

input signal and the output bus, as well as the multi-input element NAND. The device remains operable when exposed to it (via the power bus or the input signal) of random or periodic impulse noise, if their duration does not exceed (where if is the duration + t

it's t

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clock pulse duration, t is the shift between clock pulses). and the frequency of the individual pulses of interference is less than the frequency of the clock of pulses 23. However, when exposed to a device of a longer duration of interference, which can lead to the failure of all trigger cells, the probability of issuing a false output information remains high enough. The purpose of the invention is to improve noise immunity. This goal is achieved by the fact that the device for synchronizing pulses, containing an input signal bus, two buses of clock pulses, an RS trigger, two clocked triggers, two two gate elements, AND-NOT, the first multiple-input element, IS-NOT, the first three inputs of which are connected respectively to direct outputs of clock triggers and to the second bus are duty pulses, and output to the first input of the RS flip-flop, the R-input of which is connected to the input bus, and outputs to the information inputs of the first clocked trigger, whose outputs With the same information inputs of the second. trigger, the inputs of the first two-input element AND-NOT are connected to the input bus and the second bus of the clock pulses and the output to the counting input of the second triggered trigger, the second multi-input element is AND-NOT, two elements NOT, two two-input element And and sensor-interference, for example, a clocked trigger, the information inputs of which are cross-connected to the outputs, and the first three inputs of the second multi-input element AND-NOT are combined with the first three inputs of the first multiple one-AND-NOT element whose fourth input is connected to the inverse output of the noise sensor, the direct output of which is connected to the fourth input of the second multiple-input element AND-NOT whose output is connected to one of the inputs of the second two input element AND-NOT whose output is connected to the output bus and the other input through the first element NOT to the output of the first multi-input element NAND, the first bus is connected to the counting input of the first clocked trigger, the second clock bus through the second element NOT to the installation input of the interference sensor, (The installation inputs of the clocked trigger 5 are connected respectively from the output of the W elements I, the first inputs of which are connected to the input bus, and the second inputs are connected to the additional installation input of the RS flip-flop and to the inverse output of the interference sensor. FIG. 1 shows a functional diagram of the device; in fig. 2 time diagrams. The device for synchronizing pulses contains RS-flip-flop 1, first-clocked trigger 2, second-clocked trigger 3, first and second multiple-input elements AND-NO 4 and 5, first and second two-input elements AND-NOT 6 and 7, first and second elements NO 8 and 9, the first and second elements And 10 and 11, the sensor 12 noise, the input bus 13 asynchronous signal, the first bus 14 clock pulses, the second bus 15 clock pulses, the output bus 16.. The device works as follows. In the absence of an input signal and external interference, the device is in a steady state, while the R-input of the RS flip-flop 1 receives a logical O signal, therefore, its inverse output has a potential of logical 1 (fig.2d). Thus, the information inputs 3 and K of a clocked trigger 2 are the potentials of logical 1 and logical O, respectively. Despite this, clocked triggers 2 and 3 do not switch when clock pulses are received from buses 14 and 15, since the potential of logical O from input bus 13 through elements 10, 11 is fed to the R inputs of these triggers and keeps them in the initial state (FIG. .2 e, g). Multiple-input elements AND-NOT 4, 5 are blocked by logic signals O, coming from the direct outputs of the flip-flops 2 and 3 (Fig. 2 l, m), and the signal 1 is present on the bus 16 of the device (Fig. 2 n). From the inverse output of the sensor 12 noise on the element AND-NOT 4, the signal is logical 1, and from the direct output to the element IS-NOT 5, the signal is logical O (Fig. 2) because the clock pulses on the bus 15 through the element 9 the interference sensor 12 is held on the R input in its original state. When a logical 1 signal appears on the input bus 13 at the outputs of the elements And 10, 11 (Fig. 2, s), the signals of logical 1 appear. Therefore, the clock pulse coming from the bus 14 switches the clocked trigger 2 (Fig. 2 e ). The potentials at the information inputs of the clocked trigger 3 change accordingly, the clock pulse from the bus 15 passes through the input signal element AND-NE .6 to the counting input of the clock trigger 3 and switches it (the leading edge). Thus, at the three inputs of the NAND 4 element there is a logical 1 signal and, arriving at its fourth input, the clock pulse from the bus 15 passes through the NAND element 4 and switches to the S input, RS flip-flop 1, the potentials on the information inputs trigger 2. At this element, AND-NOT 5 is locked with a logical O signal from the direct sensor output

12 interference and at the output of the element IS-NOT 5 there is a logical 1 (Fig. 2 m). The clock pulse that appeared at the output of the element AND-HE 4 (Fig. 2 l) is inverted by the element HE 8 and passes through the open element AND-HE 7 to the output bus 16 of the device (Fig. 2 n). The next clock pulse from bus 14 switches the trigger

2 in the initial state, thereby changing the potentials at the information inputs of the trigger 3. Clock pulse

from the bus 15 switches the trigger 3 to the initial state (Fig. 2 g). Thus, for one input signal form1 "O1 one clock pulse. When the input signal is terminated by a logical O signal via the input bus 13, the triggers 2 and 3 are confirmed in the initial state, and the RS flip-flop 1 switches the potentials on the information inputs of the trigger 2 (Fig. 2 d). The device is ready to receive the next input signal. When exposed to external interference, the likelihood of latching triggers 2, 3 and the appearance of false information at the output of the AND-NOT element 4 increase dramatically, especially for durations of interference greater than t + 1 st. The introduction of the interference sensor 12, in which the counting input (the start input) is free, makes it impossible to pass; the false information is output to the device output while the clocked trigger 2 fails and

3from external interference.

Consider three cases:

1. Long interference arrives at the input bus 13 and knocks down triggers 2, 3 and RS-flip-flop 1 (FIG. 2 d, e, g). Simultaneously, the sensor 1 interference (Fig. 2 g). Although the interference induced onto the input bus 13 is perceived by the device as a useful signal, the logical O signal from the inverse output of the sensor 12 blocks the NAND 4 element and through the elements

And 10, 11 is applied to the R-inputs of the triggers. 2 and 3, by setting and holding them in the initial state. This signal is at the input of $ 2 reals, nodding RS flip-flop 1 in the state of logical 1 (at the Q output). Thus, the clock pulse from the bus 15 cannot pass to the output of the element NAND 4. This clock pulse through the element NOT 9 returns the sensor 12 to the initial state. . The clock pulses from the buses 14, 15 all the time confirm the initial states of the flip-flops 2 and 3, as long as the potential on the input bus 13 is present.

2. The external interference is affected by the presence of a useful signal on the input bus 13. In this case, the useful signal is split up (FIG. 2c). If a

By this time, the triggers 2 and 3 are switched to the working state, and a useful signal appears at the output of the IS-NO-4 element (Fig. -2 L), then the disturbance transfers the triggers 1, 2 and 3 to the initial state. However, sensor 12 triggers this, the output of which sets the RS-flip-flop 1 to state 1, locks the AND-NE element 4 and keeps the trigger 2 and 3 in the initial state. In this case, the occurrence of false information is excluded if the duration of fragmentation is greater than t-, + t.

0

3. When the inverted output of the sensor 12 is broken and when exposed to external interference, false information passes to the output. To avoid this, there is a second element AND-HE 5, to the inputs of which the signals from the direct outputs of the flip-flops 2, 3 and the sensor 12 and the clock pulse from the bus 15 are fed.

Thus, the false pulse that appeared at the output of the element AND-NOT 4

0 and the pulse from the output of the element AND-NOT 5 are simultaneously applied to the BAN element consisting of the element HE 8 and the element AND-NOT 7. At the same time, the appearance of false information on the output bus 16 is eliminated.

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Thus, the proposed device is self-correcting during and after exposure to external interference, i.e. detects interference and corrects trigger failures, and in

0 individual cases (with breaks) corrects the error.

Claims (2)

1. USSR author's certificate No. 606200, cl. H 03 K 5/13, 03.05.76. 2. USSR author's certificate No. 607343, cl. H 03 K 18/42, 08/30/74. 1 L.L: U U u "41