SU1176332A1 - Device for detecting failures of synchronized digital system - Google Patents

Abstract

I WILL SET UP FOR THE DETECTION "(ENERGY OF FAILURES OF SYNCHRONIZABLE DIGITAL SYSTEM, containing the element OR NOT, h. Control nodes, each of which contains a trigger, the first element IS, NOT the first element AND, the display element, and in each control unit the inputs of the first element AND are respectively synchronization and control inputs of the control unit, the output of the first element I-PE is associated with the trigger trigger input, characterized in that, in order to expand the functionality of the device by determining the number of transitions at failure x, caused by logic ratios, a second element AND, a second element AND –NE, a counter, two single vibrators are entered into each control node, the inputs of the single vibrators are combined and connected to the output of the corresponding control unit, the outputs of the first and second single vibrators are connected to the corresponding inputs of the second element And, the output of which is connected to the counting input of the counter, the reset input of which is connected to the input of the initial installation of the device, the synchronizing input of the counter connected to the output of the first element And, the outputs are The counter's inputs are connected to the corresponding i inputs of the second NAND element and to the inputs of the display element, the output of the second g (of the Third NI element is connected to the first C input of the first NAND element, the second input of which is connected to the sync input the control unit, the trigger trigger input is connected to the initial setup input of the device, the trigger setup input is connected to the inverse trigger output, the direct output of which is connected to the corresponding input of the IPI-NE element, the output of which is controllable by the device output -keeping.

Description

The invention relates to automation and computer technology and can be used to diagnose digital systems for failure.

The purpose of the invention is to expand the functionality of the device by determining the number of transitions in the event of a breakdown caused by the logical characteristics of the signals.

The drawing shows a block diagram of a device for detecting the occurrence of failures of a synchronized digital system.

The prepaid device for detecting the occurrence of failures contains an OR-NOT 1 element, control nodes 2, a controlled system synchronization block 3, a controlled system blocks 4, two single-generator 5 and 6, a binary counter 7, trigger 8, elements 9 and 10, the first element of the IPE 11, second IS-NOT 12, display unit 13, synchronization input 14 of node 2 controls, input 15 controls of node 2 controls, information input 16 of node 2 controls, input 17 of the initial settings of nodes 2 controls output 18 of the device, input 19 of the initial installation of the device .

The proposed device is intended to detect failures that occur, in particular, due to logical concurrences. digital synchronized systems. In case of their criticality, they are accompanied by brief changes in the output signals of the blocks during the operation of the sync pulse, i.e. the output signal does not remain unchanged during the operation of the sync pulse, but varies either as 1-0-1 or 0-1-0. The principle of operation of the proposed device is based on the detection of such transitions and counting their number.

The device works as follows.

At the beginning of the work on the input 17 of the initial installation of the device, all the control units 2 are set to the initial position. The counter is reset to the zero state. At the direct output of the trigger, O is set, and at the inverse output and the enable input V, 1 is set, putting the trigger into the open state. On the code element H-NE 11 is set to 1, at the output of the element IS-NOT 12 l of the counting input of the trigger is set O. Signals 1 are set by the element ILINE 1 on all inputs 15 of the control nodes 2 of the control.

If there are no failures in the digital system, the device functions as follows.

From block 3 of the controlled system synchronization, one of the working blocks 5 of the controlled system and one of the 2 control units receives a clock pulse. At the output of block 4, a signal 1 or O is set up along the leading edge of the clock pulse. This switching in a serviceable system takes place with some delay, but then no changes occur at the output in the process of the clock pulse action. The arrival of a sync pulse (signal level 1) at the input 14 of the synchronization node of the control causes the appearance of signal 1 at the output of the AND 9 element, which puts the counter 7 in the open state. For this reason, it becomes possible for the counter 7 to react to a change in the signal at the counting input, which is connected via an IU element 11 and two one-vibrators to the information input 16 of the control unit 2. In case of correct operation of block 5, the signal O is present at the counting input of counter 7, because signals 1 arriving at the inputs of element 10 from the outputs of one-vibrators 5 and 6 do not appear simultaneously, since one single-oscillator signals signal 1 of a certain duration fco by switching the signal to input from O to 1, and the other - Gso from 1 to about. D since the duration of the SOSIGIG at the outputs of the one-shot is chosen from the dependence C "T,

f duration sync signal

That is achieved by appropriate adjustment of single vibrators by connecting RC elements to the corresponding outputs, then when unit 4 is working properly, signal 1 of duration T (; p "appears when switching the output of unit 4 on the leading edge of the sync signal when the signal at the output of block 4 is switched, for example, from 1 to O, and at another at some other moment of time also when the leading edge of the sync pulse appears, switching from O to 1 is possible in the next clock cycle or after a few clock cycles of the impact of the clock pulses, which depends on the logic of the operation of block 4.

Thus, normal changes or signals at the output of block 4 during normal operation occurring under the effect of clocking sync signals do not arrive at the counting input of counter 7, since the duration of the fj.p sync signals is much longer than the duration of the signals at the one-shot outputs 5 and 6. Hence It can be seen that in the absence of failures in the digital CW -

On the subject, the state of all nodes 2 controls is unchanged.

In the event of a failure in the digital system, a synchronization impulse is received from one of the working units 4 and one of the 2 control units in the synchronization block 3 of the controlled digital system, as before. But in this case, at the output of block 4, the signal is not set to an unambiguous state on the leading edge of the clock, but changes from O to 1, or vice versa, possibly many times. With this change of signals from O to 1, the first one-shot 5 at its output produces a signal 1 with a duration of fco, and when the signal changes from 1 to O, another one-shot 5 gives rise to a signal 1 with a duration of f, while the signals of failures appear as signal surges or in other words, in the form of needles, and have both a leading edge and a slice, signals 1 from the direct outputs of the one-shot 5 and 6 overlap in time, and for the duration of the overlap at the output of the And 10 element appears signal 1 with a duration equal to overlap signals 1 from direct outputs one Rotary. Signal 1 is fed to the counting input of counter 7, which counts the number of transitions 0-1-0 or 1-0-1. The first such transition causes the occurrence of 1 at one of the outputs of the counter (in the lower order), this causes the switching element AND-NOT 11, and at its output a signal O appears. From this moment on, further state changes counter 8

when counting the number of transitions discussed earlier, the state of element H-NOT 11 cannot change, since at least one of its inputs there is a signal 1 for any state of counter 7 in counting mode C of the output of element H-NOT 11, the signal O arrives at the first input of the element AND-NO 12, however, the switching of the element AND-NO 12 does not occur, since at its second input there is a signal of 1 clock pulse. For this reason, the trigger 8, the input of which is connected to the output of the element AND-NO 12, cannot be switched and is in the initial state. As soon as the sync pulse completes, which is equivalent to the occurrence of signal 1 at the synchronization input 14 of node 2 of the control, at the output of element 9, a signal O appears, which arrives at the enabling input of counter 7, as a result of which counter 7 stops responding to signals arriving at his counting entry. At the same time, the signal O from the synchronization input 14 of the node 2 of the control arrives at the second input of the EEI element 12 and triggers the trigger 8, a signal 1 appears at its direct output, and in the inverse. Since the inverse output of the trigger 8 is connected to its control input V , then the trigger goes to the closed state and stops responding to the signals coming to its input T. Signal 1 from the direct output of trigger 8 goes to the corresponding input of the IGSh-HE element 1 and causes it to switch, and the signal O from its output enters the input of 15 control manifestations of nodes 2 controls. At the outputs of the elements And 9 sets the signal O, which arrives at the control inputs of the counters 7, as a result they cease to respond to the signals arriving at their counting inputs. The states of the counters 7 display the display block 13.

From output 18 of the device, the signal can be reversed. It can transmit to the control unit of the digital set to fix the cycle in which the failure occurred.

Claims (1)

DEVICE FOR DETECTING FAILURES OF A SYNCHRONIZABLE DIGITAL SYSTEM containing an OR-HE element, h. control nodes, each of which contains a trigger, the first AND element, the first AND element, an indication element, and in each control unit, the inputs of the first AND element are, respectively, the synchronizing and control inputs of the control unit, the output of the first AND element is NOT connected to the clock input trigger, characterized in that, in order to expand the functionality of the device by determining the number of transitions in case of failures caused by logical competitions, the second element And, the second element, are introduced into each control node -NOT, a counter, two single-vibrators, the inputs of the single-vibrators combined and connected to the output of the corresponding control unit, the outputs of the first and second single-vibrators connected to the corresponding inputs of the second element AND, the output of which is connected to the counter input of the counter, the reset input of which is connected to the input of the initial device settings, the synchronizing input of the counter is connected to the output of the first AND element, the outputs of the bits of the counter are connected to the corresponding inputs of the second element AND NOT and to the inputs of the indication element, W output -: the horn of an AND-NOT element is connected to the first input of the first AND-NOT element, the second input of which is connected to the synchronizing input of the corresponding control unit, the trigger trigger input is connected to the device initial setup input, the trigger setting input is connected to the inverse trigger output, whose direct output connected to the corresponding input of the OR-HE element, the output of which is the control output of the device. > 1 .1176332 2