SU1683173A1 - Converter of asynchronous pulse sequence to binary code - Google Patents

Abstract

The invention relates to a pulse technique. The purpose of the invention is the expansion of the field of application of information due to the fact that the device containing a pulse counter 1 and a frequency divider 2 introduced the second frequency divider 6, triggers 7 and 8, inverters 9, 10 and 14, triggers 11 and 12, elements 13 and 14 accumulating adder 17. This makes it possible to reliably and with great accuracy count the number of pulses of an asynchronous sequence. 2 Il.

Description

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The invention relates to a pulse technique and can be applied in automation and computing devices.

The purpose of the invention is to expand the scope.

Figure 1 shows the functional diagram of the device; FIGS. 2 are time diagrams for the operation of the device.

The converter contains a pulse counter 1, a frequency divider 2, an information sequence bus 3, a processing period bus 4, a clock frequency bus 5, a frequency divider 6, D-flip-flops 7 and 8, inverters 9 and 10, D-flip-flops 11 and 12, And elements 13 and 14, inverter 15, accumulation period setting bus 16, accumulating adder 17.

The Converter operates as follows.

The pulses of the asynchronous information sequence (Fig. 2, plot 2) from the bus 3 of the device are fed to the fault inputs of frequency dividers 2 and 6, setting all their outputs to state O. After the action of the pulse R has expired, both frequency dividers start to divide the frequency of the FT clock pulse frequency (3-5) Pu supplied to the counting input (plot 1). In this case, the frequency divider 6 stops dividing after the appearance at its third output of logic 1, which blocks further operation of the frequency divider for a given period of the information frequency P. In this case, at the second output of the frequency divider 6, only one pulse is generated

2 Gu-p-, which is an ingi pulse

formation sequence synchronized frequency F, and which is fed to the counting input of the information counter 1 (Fig. 2, plot 5). The frequency divider 2 after the end of the pulse F operates in the continuous mode of frequency division until the period of the next information pulse frequency Re.

Divider 2 frequencies for the time between two frequency pulses forms two impRt Pg pulse sequences of PGI CG.

which, respectively, from the first and second outputs are supplied to the clock and information input of the trigger 7 (Fig. 2, plots 6 and 7). As a result, at the output of trigger 7, in the period between two pulses of the information sequence Re, a sequence of pulses is formed

duration

FT

shifted in relation

the sequence to the counting input of the counter 1 for the delay time - (figure 2,

(-t

plot 8).

Sequence with trigger output

7 is used to form a pulse

"I Write the processed information for (figure 2, plot 14) from counter 1 to the accumulating adder in the presence of a signal permitting the accumulation of a pulse Reset collected in the counter information for time J

Fo

The formation of these pulses is as follows.

Negative differential frequency F0 is synchronized by negative differential of clock frequency Рт with the help of trigger 8 and inverters 9 and 10. With the help of the circuit implemented on triggers 11 and 12, the synchronized negative differential of frequency P0, indicating the end of the processing time, is converted by pulse from trigger output 7 at trigger output 12

2

in a pulse of duration p-bound at the end of the treatment period. With the help of logic circuits this

2 single pulse duration -F-,

Rm

indicating the end of the processing period is divided into two pulses of duration F-(Ha pulse Reset by you-

during the element And 13 and the impulse Record at the output of the element And 14).

Pulse Recording rewrites information from the counter to the accumulating adder 17. Accumulation occurs over time, determined by signal 16, and the reset pulse resets the counter and prepares it for the next processing period. As follows from the diagram, impulse 1 of the information sequence for the period T0 | attributed to

information for the period Tom, and for the period

the counter counts only pulses 2

and 3. For the time interval Tom - T0 | at

the accumulating adder is fixed

1 all impulses without loss.

The positive effect of the application. The proposed converter is that when processing an asynchronous pulse sequence, the accuracy and reliability of information processing is improved. Etb is achieved by

Claims (1)

expanding the functionality of the converter, allowing it to convert both a synchronous and an asynchronous pulse sequence to binary code. Claims of an asynchronous pulse sequence converter into a binary code containing a pulse counter and a frequency divider, characterized in that, in order to expand the field of application, a second frequency divider, four D-triggers, three inverters, two AND elements, accumulating adder, whose outputs are the output bus, the information inputs are connected to the corresponding outputs of the pulse counter, and the synchronization input is connected to the output of the first And element, the first input of which is combined with the first input of the element I, the installation input to the first trigger and connected to the output of the second D-trigger, the synchronization input of which is connected to the output of the third D-trigger, and the information input to the output of the first D-trigger, whose information input is the bus of the corresponding and the synchronization input with the fourth trigger output, whose information input through the first inverter is connected to the processing period bus, and the slot input “The second inverter is often connected to the input synchronization of the first and second dividers s is the clock frequency bus, the second input of the first element I is the accumulation period setting bus, and the third input is combined with the input of the third inverter, the synchronization input of the third trigger and connected to the first output of the first frequency divider, the second output of which is connected to the information input of the third trigger, and the setup input in O is combined with the same input of the second frequency divider and is an information pulse train, the gate input of the second frequency divider is connected to the first swing second frequency divider, the second output of which is connected to the counting input of pulse counter, the input setting of G is connected to the output of the second AND gate, a second input coupled to an output of the third inverter. mnjummjijwuijw 12345 PLP Bw (Cxtfu-LJTjnjlJUTJlJlJ lJnJl rLnj FJ TjmrmrtrinruTjTjmjTjTj