SU1675919A1 - Device for transmitting data through fiber optic communication line - Google Patents

Abstract

The invention relates to fiber optic information transmission systems. The goal is to increase the reliability of transmission and reduce energy consumption. Information transfer is carried out after preliminary interrogation of the communication line connecting the analog and discrete sensors 14i-14n, 15i-15i and multiplexers 18, 19, 20, 21. In the short circuit (break) in the communication line, the threshold elements 27-30 trigger. which prohibit the passage of a signal to the transmitter and form a signal of the emergency state of the communication line. The device contains on the transmitting side 1. power unit 2, shaper of reset signal 3, shift register 4, element EXCLUSIVE IL AND 5, element NOT 6, element AND 7, clock frequency generator 8, frequency divider 9, transmitter 10, fiber-optic line communications, keys 22-25, analog memory elements 33,34, trigger 26, OR elements 31, 32, memory elements 35. 36, analog key 37, groups of shunt elements 38, 39, groups of isolating elements 40-45 , restrictive elements 46, decoupling elements 47, block 48 matching. On the receiving side there are a shift register, a buffer register, an address decoder, a write pulse shaper, a receiver, an EXCLUSIVE OR element, an AND element, a frequency divider, a register, a DAC, a display unit, a register, and correction blocks. 2 Il. w 0 0 VI eaten o

Description

The invention relates to fiber optic information transmission systems and can be used in automated equipment control systems.

The purpose of the invention is to increase the reliability of information transmission and reduce energy consumption.

 la fig. 1 and 2 show a structural block diagram of the device.

The device contains on the transmitting side 1 power supply unit 2, a reset signal generator 3, a shift register 4, an EXCLUSIVE OR 5 element, a HE element 6, an AND 7 element, a clock frequency generator 8, a frequency divider 9, a transmitter 10 consisting of a code converter 11 and electro-optical converter 12, fiber-optic communication line 13, analog 14 and discrete 15 sensors, counter 16 addresses and analog-to-digital converter 17, analog 18 and 19 and digital 20 and 21 multiplexers, keys 22-25, trigger 26 , threshold elements 27-30, elements OR 31 and 32, elements 33 and 34 analog memory, memory elements 35 and 36, analog key 37, groups of shunt elements 38-38n, ..., n, groups of isolating elements 40-45, first limiting elements 46, isolating elements 47, block 48 matching , on the receiving side 49, a shift register 50, a buffer register 51, an address decoder 52, a write pulse shaper 53, a receiver 54 containing an optoelectric converter 55 and a code converter 56, an EXCLUSIVE OR 57 element, an AND 58 element, a frequency divider 59, a register 60, digital-to-analog converters 611-61 p. Block 62 indie atsii1, the register 63 and the correction blocks.

The device works as follows.

When block 2 is turned on, the signal through the driver sets the elements 33-36, trigger 26, address counter 16 and frequency divider 9 to the initial state. A clock frequency generator 8 is turned on, generating pulses with a fixed frequency, which are fed to the input of frequency divider 9. From frequency divider 9, pulses of frequency 2f arrive at the clock input of converter 1.1, from the third output — pulses of frequency f arrive at matching unit 48 (for example, a transformer) and clock input of shift register 4, from the fourth output — pulses of frequency f (N + 1) the elements are EXCLUSIVE OR 5 and at AND 7, from the second output - faun pulses are fed to the clock input of the analog-to-digital converter (ADC) 17, and Tac is selected so that the block conversion time is less than or equal to the duration of the register 4. If there is a logical O at the mode setting input, the 4th shift register operates in the sequential input mode, From the 4th register output, the serial code goes to the EXCLUSIVE OR 5 element, and from this element output to the serial 4th register input. OR 5 pulse frequency f (N + 1) from the fourth output of the divider 9 corresponding bit

5 of the sequential code is inverted. Upon receipt of the same pulse on the element And 7 simultaneously with the presence of logical 1 at the output of the shift register 4 at the output of the element And 7, a pulse is formed

0 which transfers the 4 shift register to the parallel input mode, with the last bit of the register being recorded as a logical 0, which is fed to the last parallel input of the register 4 s

5 output element NOT 6.

Thus, the cycle of operation of the parallel-serial register 4 of the shift contains 2 (NM) bits of information, with the first but the second half of the cycle the first number of bits are identical, and the last one, which plays the role of a clock pulse, is inverted - in the first half of the cycle, the clock pulse is transmitted logical Oh, and in the second - logical 1.

5According to the above on

element output 7 forms pulses with the following frequency f / 2 (N + 1), which translate the register into parallel input mode, and also trigger ADC 17, go to counter 16 and to trigger 26. The trailing edge of these pulses changes code combination at the output of address counter 16, which is fed to the sixth input of register 4, as well as the address inputs of digital 20 and 21

5 and analog 18 and 19 multiplexers.

In this case, according to a given program, information is collected from sensors 14 and 15 and the state of the communication line is polled. So, at time ti, it interrogates the communication link connected to analog sensor 12g via the circuit: power supply unit 2, switch 24, elements 312, 44i and the first input of analog multiplexer 19 and transmission of information from sensor 14i through

5 open elements 43i, 45i to multiplexer 18, From the output of analog multiplexer 19, the voltage goes to elements 27 and 28, where the signal is compared with the threshold. In the event that a short-circuit type fault (open circuit) has occurred in the communication line, the multiplexer 19 receives (does not receive) the voltage D of the power supply unit 2 along the above circuit. In the event of a short circuit (open circuit), element 27 (28) is triggered, in which the signal is compared with the threshold and a signal appears at its output. When a pulse 1/2 f (N + 1) arrives, information is recorded in element 33 (34), switching of trigger 2.6 and address change, trigger 26 turns off keys 24 and 25 and turns on keys

22 and 23. The key 22 connects the second analog input of multiplexer 18, the third output of block 2 and analog sensor 142 to the circuit, and the key 23 to the second input of analog multiplexer 19 to the second output of power supply 2. In the case considered above, there was a violation of the short circuit type (open circuit) in the communication line, therefore the signal from the sensor 142 does not reach the multiplexer 18 and at its input there may be electromagnetic pickups or an incomplete signal that goes to the key 37. However, with the arrival of an impulse 1/2 f (N + 1) key 37 is locked with a signal received from element 27 (28) through the element OR 31. Thus, the input of the A / D converter 17 is blocked, and O from the output of the element OR 32 is blocked at the input of the shift register 4, to the register 4 enters 1, fixing a violation in the communication line. In the second cycle, the line is checked, connecting the sensor 14 and the third input of the multiplexer 19,

In the absence of a signal at the outputs of elements 27 and 28 at the moment when a pulse 1/2 f (N + 1) is received, logical O will be written to elements 33 and 34. A logical signal O at the output of the IL element 31 opens the key 37 and removes the signal in the previous cycle the faults of the communication line go to the seventh input of register 4. At the same time, the analog signal from the output of the sensor 14z via the key 37 goes to the A / D converter 17 and, after being converted to a digital code, is fed to the fifth input of the shift register 4. Further, upon receipt of a pulse of 1/2 f (N + 1), the operation cycle of the device is repeated.

In the event that the number of inputs of the multiplexer 6 n is greater than the number of sensors 14 on the nm inputs of the multiplexer 19, for example, 46 /, 4bz and elements 48i, 48a are energized from the keys 23 and 24. Moreover, the odd inputs are connected to the outputs of the keys 22 and 24, and odd inputs - to the keys

23 and 25. The voltage applied to elements 27 and 28 is less than the short circuit setting and greater than the setting. Breaking the link does not trigger the thresholds.

devices and the shift register 4 will not receive a signal to break the communication line.

For time t1, it is also characteristic that from now on during the cycle the communication line is interrogated and information is transmitted from discrete sensors 15i-15. At the same time, from the first output of the block 48, the positive half-cycle of the clock frequency through the elements 382 and the diode 411 goes to the first input of the multiplexer 21, and the negative one from the second output of the block 48 through the elements 45 and 44 and the closed contact of the sensor 15 to the first input of the multiplexer

20, Thus, during a single clock cycle, a signal is transmitted about the state of the 5th sensor 15i and monitoring the communication line connecting the sensor 152 and the multiplexer

21. The signal from the output of the multiplexer 21 arrives at elements 29 and 30, in which it is compared with the setpoint at

0 short circuit and open circuit. In the case of a short circuit (open circuit) in the communication line, element 29 (30) is activated and the signal from its output goes to element 35 (36). When a pulse arrives with

5, a driver 43 (containing, for example, a d-chain, a rectifier and a key) information is recorded in element 35 (36). From the output of element 35 (36) logical 1 through the element OR 32 enters the register 4,

0 on the corresponding position is recorded information about the state of the communication line. Simultaneously with the arrival of 1 to the input of the element OR 32, the control input of the element 42 receives a signal prohibiting the passage of information from the output of the sensor 142 through the multiplexer 20 to the shift register 4. In the next cycle of the first cycle, the second sensor is polled and the communication line connecting the sensor 14z to the multiplex 21.

When the number of sensors K is less than the number of multiplexer 20 -K information inputs of multiplexer 21 through sequentially connected elements 46 and 47 are connected to block 48, and odd inputs to the first output, and even to the second. In this case, at the corresponding clock cycles, the signal from block 48 through elements 46s, 46e, 474, 47s and multiplexer 21 goes to

0 elements 29 and 30. Since the voltage value differs from the short circuit setting and line break, the output of the elements 29 and 30 lacks a signal and, therefore, the seventh input of register 4

5, the shift will not receive a signal of violation in the communication line. In the next cycle, a sequential polling of the sensors and the communication line is performed similarly to the previous cycle. Multiplexed

The signals from the 15i-15n sensors from the output of the multiplexer 20 come to the sixth input of the shift register 4.

From the output of register A, the serial code is fed to the information input of the converter 11, to the clock input of which pulses are applied with a frequency of 2f from the first output of the divider 9. The converter 11 performs the conversion of the serial code without returning to zero a linear self-synchronizing code - th transducer 12, converts electrical signals about optical. The optical signal from the output of the electro-optical converter 12 through the fiber-optic cable 13 is fed to the input of the optical-optical converter 55, which performs the inverse conversion. From the output of the optoelectric converter 55, a linear self-synchronizing code is fed to the input of converter 56, which converts it to a serial code without returning to zero and selecting a clock frequency. The serial code and clock pulses from the output of converter 56 are fed to the corresponding inputs of register 50, which has Mn -2 parallel outputs, and thus, at its first and last outputs simultaneously, there will be bits of a code parcel with the same sequence numbers. In the EXCLUSIVE OR 57 element of block 53, a one-by-one comparison of the corresponding bits of the code message from the first and second parts of the transmission cycle occurs. When they are non-identical, logical 1 appears at the output of the EXCLUSIVE OR 57 element, and with the arrival of the next clock pulse, logical 1 also appears at the first output of register 60 and divider 59 is reset to O, and at the output of divider 59 logical 1, only 1 if the N bits in the first and second half of the transmission cycle will be identical.

With the arrival of a clock pulse, which is constantly inverted, the logical 1 appears at the outputs of the EXCLUSIVE OR 57 element and the divider 59, and, therefore, the And 58 output also. With the arrival of the next clock pulse, a write pulse is generated at the output of register 51, the information from the first outputs of shift register 50 is rewritten into register 51. If there is an error in the code message — one of the information bits in the first and second parts of the transmission cycle does not match — the records Register 51 does not occur. From the second exit

register 51, the address code is fed to the input of the decoder 52, which distributes the write pulses to register cells 63 and the converters 61i-61n.

 The information output of register 63 is connected to the third output of register 51. In accordance with the address code, information from this output of register 51 is recorded in certain cells of register 63 and stored on its outputs during the cycle of changing the address code. From the first output of the register 51, information is fed to the information inputs of the converters. In accordance with the address code, the information is recorded in the register of a specific 55i-55n converter, converted into an analog signal, and through the block enters the display panel or the actuator (installed at the monitored item). The unit subtracts the voltage that was used on the transmission side to eliminate the effect of the 38i-38n elements on the transmission

5 analog signals from sensors to multiplexer 18.

In the presence of a signal break (short circuit) of the communication line, the operator can timely detect the fault and

0 in the subsequent analysis to determine which group of sensors (analog or discrete) should include this fault. Such a solution makes it possible to eliminate emergency situations that occur during the transmission of analog and discrete information, for example, about the level of methane concentration.

Claims (1)

Formula of the Invention 0 fiber-optic communication line, containing on the transmitting side analog and discrete sensors, shift register, clock frequency generator, the output of which is connected to the input of a frequency divider, the first 5 whose output is connected to the first input of the transmitter, the second output is connected to the first input of the EXCLUSIVE IL AND element and the AND element, the third output is connected to the input of the analog-digital converter, the fourth output is connected to the first control input of the shift register, the output of which connected to the second input of the EXCLUSIVE OR element, AND element, transmitter and through the NO element to its second control input, the output of the EXCLUSIVE element OR is connected to the third control input of the shift register, the output of the AND element is connected to control register input, control input analog-digital the converter and the address counter input, the first digital and analog multiplexers, the transmitter output is connected to the fiber-optic communication line input, on the receiving side - the receiver, whose input is connected to the fiber-optic communication line output, the first receiver output is connected to the information input of the register the shift and the first input of the write pulse former, the information inputs of which are combined with the corresponding inputs of the buffer register and connected to the corresponding outputs of the shift register, the first output buffer The real register is connected to the input of the address decoder, the second and third outputs of the buffer register are connected to the integrated information inputs of digital-to-analog converters and the register input, each of the outputs of the address decoder is connected to the input of each digital-to-analog converter and the corresponding information input of the register, the output of which is connected to the input of the display unit, characterized in that, in order to increase reliability and reduce energy consumption, a power supply unit is inserted into the transmitter side input elements, groups of shunt elements, second digital and analog multiplexers, matching unit, analog memory elements, trigger, prohibition element, pulse driver, analog key, memory elements, OR elements, keys, reset signal generator, restrictive elements, development groups elements, the first output of each discrete sensor is connected to the first output of the corresponding shunt element of the first group and through the corresponding decoupling element of the first group is connected to the corresponding the first digital multiplexer information input and through the corresponding decoupling element of the second group to the corresponding information input of the second digital multiplexer, the second output of each discrete sensor is connected to the second output of the corresponding muting element of the first group through the corresponding first restrictive and isolating elements - with the corresponding address input of the first digital o multiplexer, the output of the first analog multiplexer is connected respectively via the first and second threshold elements to the first inputs of the first and second elements of the analog memory t-l, (the output of the first discrete multiplexer is connected, respectively, h .: the third and fourth threshold elements are cut to the first inputs of the first and second memory elements, the first output of the power supply unit is connected via a reset signal shaper to the installation input of a frequency divider, a trigger, memory elements, an address counter, analog memory elements, 0, the outputs of the first and second elements of the analog memory are connected respectively to the first and second inputs of the first OR element, the output of which is connected to the first input of the analog key and the second epemen 5 ha OR, the second and third inputs of which are connected to the outputs of the first and second memory elements, respectively, the outputs of the second element a OR and the analog-digital converter are connected respectively to the first and second convergence of the shift register, the output of the address counter is connected to the third input of the shift register and the control input n The first and second analog and digital multiplexers, the output of the second digital multiplexer is connected to the direct input of the prohibition element, the inverse input of which is connected to the output of the second memory element, the output of the prohibition element is connected to the fourth input of the shift register, the second outputs of all shunt elements of the first group connected to the corresponding outputs of the matching unit and through the pulse shaper to the second input of the first and second elements 5 memory, the output element And is connected to the trigger input and the second inputs of the analog memory elements, the output of the second analog multiplexer is connected to the second input of the analog key, the output of which 0 is connected to the information input of the analog-digital pre-razoezotel, the fourth output of the frequency divider is connected to the input of the matching unit, the direct inverse outputs of the trigger are connected to the first inputs of the first, second, third and fourth keys, respectively, the second and third outputs of the power supply unit are connected to the second the inputs of the first, fourth and second, respectively, the third; o key, the first output of each analog sensor is connected to the first output of the corresponding shunt element of the second group and through the corresponding decoupling element of the fourth group 5 - with the corresponding information input of the first analog multiplexer and through the corresponding decoupling element of the fifth group - with the corresponding information input of the second analog multiplexer, the second output of each through the analogue decoupling element of the sixth group, an analog sensor is connected to the second output of the corresponding shunting element of the second group, the output of the corresponding key and the serially connected second limiting and decoupling elements — to the corresponding address input of the second analog multiplexer; each digital-to-analog converter through the corresponding correction block is connected to the corresponding information th input display unit. Fig 2