SU1275509A1 - Device for transmission and reception of telemetering information - Google Patents

Abstract

The invention relates to telecommunications and can be used with adaptive telemetry systems where the transmission of information with compression is required. The device at the transmitting side takes into account the order of the activity of the input channels and transmits substantial counts of messages with adaptive addressing. At the receiving side, the device restores the original messages from the transmitted substantial readings, which allows the device to be used more widely. The device contains on the transmitting side a switch, an analog-digital converter, registers, an OR element, memory blocks, comparison blocks, a counter, a block of addresses, a de-encryptor and a clock, a communication channel; on the receiving side there are memory blocks, trunk registers, an OR element, a digital-analog converter, a switch, a decoder, an AND element, a comparison block, a counter, and a clock. 1 il. Go vi JV SL

Description

The invention relates to telecommunications and can be used in adaptive telemetry systems where data transmission with compression is required. The purpose of the invention is to expand the scope of the device. The drawing shows the functional diagram of the device. The device contains on the transmitter side of the switch 2, analog-digital converter 3, the second register 4, the element OR 5, the second memory block 6, the first comparison block 7, the first multichannel; the 1st memory block 8, the counter 9, the second comparison block 10, address block 11, first register 12, channel decoder 13 HOMejja and chronizer 14, communication channel 15, and on the receiving side I 6 - the first memory block 17, first register 18, element OR 19, digital analogue converter 20, commutator 21 , the decoder 22 addresses, the second multi-channel memory block 23, the second register 24, the element And 2 5, a comparison block 26, a counter 27, and a clock 28. The device operates as follows. On transmitting side 1, information channel signals alternately through switch 2 are fed to analog-to-digital converter 3, where the analog signal is converted into a binary code, which is stored in register 4. The next sample code of the information channel is compared in block 7 with the previous significant reference code arriving from block 8, the file that switches with the switch 2 via the clock signal 14. The same clock signal 14 is fed to the input of the counter 9 of the number of the polled input Foot and increases channel state COUNT ka 9 per unit. If the next sample of the input signal does not differ from the previous significant sample, i.e. the counting is insignificant, then the signal O appears at the output of the comparison block 7, which does not allow reading the contents of register 4. If the next count of the input signal differs from the previous significant count by an amount exceeding the trigger threshold of the comparison block 7, i.e. the readout is significant, then the output of the comparison unit 7 is a signal 1, which allows reading the contents of register 4 and storing the code of this essential reference in memory block 8. At the same time, the signal I from the output of the comparator unit 7 is fed to the control (read) input of the counter 9 and the control (enable) input of the comparator block 10. In block 10, the contents of counter 9 are compared with the contents of register 12, in which the number of the previous input channel is recorded, which has transmitted a significant message to communication channel 15. If the contents of counter 9 differ from the contents of register 12 by an amount not exceeding the response threshold of comparison unit 10, i.e. the natural order of the number of input channels is not violated, then the second output of block 10 shows a signal O, which is fed to the control input of block 11 of addresses and prohibits the output of the address of the polled significant input channel. At the same time, a significant message of this input channel from register 4 through. the element OR 5 is recorded in the information part of the memory block 6. If the contents of counter 9 differ from the contents of register 12 by an amount exceeding the threshold cp: of the comparison block 10, i.e. If the natural order of the number of input channels is violated, then the second output of block 10 is a signal 1, which is fed to the input of block 11 of addresses and allows the output of the address of the polled input channel. In accordance with the number of the polled input channel on one of. the outputs of the decoder 13, a signal 1 is generated, which is fed to the corresponding input of the block 11 of addresses, which assigns the address of the polled input channel. At the same time, a significant message of the given input channel from the register 4. along with the address via the SH-5 element is recorded in the information and address parts of the 6-memory block. After comparing the content of its counter 9 with the contents of register 12, a signal 1 appears at the first output of comparison unit 10, which enters {-la input of register 12 and

permits the recording of the contents of counter 9 to register 12. Messages from memory block 6 are transmitted to communication channel 15. The code width of the information message is equal to the code width of the address message. In this case, the code combinations used for the information part of the message are prohibited for the address part of the message.

At the receiving side 16, the messages coming from the communication channel 15 are written to memory block 17 and are alternately read from memory block 17 to register 18 by signals from the clock 28. If the received message contains only the information part, the address decoder 22 does not work and a signal 1 appears at its first output, which allows reading the contents of register 18. The message from the output of register 18 through the element OR 19 enters a digital-to-analog converter 20, where a digital code is converted into an analog signal. The analog signal through the switch 21, which is switched by signals from the clock 28, is fed to the corresponding output of the device. In this case, the message is stored in the multi-channel memory unit 23, which is also switched by signals from the clock 28. If the received message contains the address part, i.e. when transmitting, some input channels are missed due to the immateriality of their messages and, as a result, the natural order of the number of input channels is violated, the decoder 22 of the addresses is triggered, the O signal is generated at its first output, prohibiting the register 18 from being transmitted.

According to the address on the third output of block 22, the code number of the input channel to which the information message belongs appears. The code number of the input channel is recorded in register 24. However, in order to fully restore the original analog signal of the missing input channels, it is necessary to give the recipients the previous common data values of the messages of these input channels that are stored in the multi-channel memory block 23. At the second output of the decoder 22

I signal appears, which enters the input of comparison unit 26 and allows comparison of the contents of register 24 and counter 27. If the contents of register 24 differ from the contents of counter 27 by an amount exceeding the trigger threshold of the comparison block 26, then the output of block 26 appears Signal 1, which is fed to the input of the multichannel memory block 23 and allows the output of the previous essential values of the messages of the missing input channels. The signal 1 from the output of the comparison unit 26 also arrives at the first input of the And 25 element. At the same time, the clock pulses of the Chroniser 28 pass through the And 25 element and switch the zones of the missing input channels of the multichannel memory block 23. At the same time, the clock pulses arrive at the counting input of the counter 27 and increase its contents. If the contents of register 24 differ from the contents of counter 27 by an amount not exceeding the response threshold of comparison unit 26, i.e. the previous significant values of the messages of the missing input channels are output, then the output of the comparison block 26 is a signal O, which prohibits the issuance of messages from the memory block 23 and the clock pulse of the chroniser 28 through the AND 25 element. -Messages from the memory block 23 also through the element 1, the 19, digital-to-analog Converter 20 and the switch 21 is fed to the corresponding outputs of the device. The next signal from the clock 28 is read the next message from the memory block 17, and the whole cycle is repeated.

Thus, the device takes into account the order of activity of the input channels and transmits messages with adaptive addressing, which reduces the bandwidth requirements of the communication channel 15. At the receiving side, the device recovers the original messages from the transmitted substantial samples, which expands the scope of application of the device.

Claims (1)

Invention Formula A device for transmitting and receiving telemetry information, containing on the transmitter side a switch whose information inputs are device inputs, the switch output is connected to the information input of the analog-digital converter, the output of which is connected to the first input of the first comparison unit and the information input of the first memory block , the output of the first memory block is connected to the second input of the first comparison block, the first, second registers, the output of the first register is connected to the first information input, the second the comparison unit of the chronizer, the first output of which is connected to the control input of the analogue digital digitizer, which is different from the fact that, in order to expand the field of application, a communication channel is entered into it, - the OR element, the second memory block TI, the counter, the decoder and the address block, the output of the first comparison block is connected to the control inputs of the second register of the second comparison block, the counter and the first control input of the first memory block, the information input of the second register is connected to the analog-digital output. The receiver is the output of the second register connected to the first input of the HJtti element whose output is connected to the information input of the second memory block, the% output of the counter is connected to the second information input of the second comparison unit, information input. the house of the first register and the input of the decoder, the first output of the second comparison unit is connected to the control input of the first register, the second output of the second block compares the outputs of the decoder respectively to the control and information inputs of the address block whose output input is connected to the second input of the OR element , the second output of the chronizer is connected to the control input of the switch, the second control stroke of the first memory block and the counting input of the counter, the third input of the raonizer is connected to the control input of the second memory block T, the output of which is connected to the input of the communication channel, memory blocks, registers, a decoder, a comparison block, a counter, a clock, an AND element, an OR element, a D / A converter and a switch, the information input of the first memory block are connected to the receiving side. the output of the communication channel, the output of the first memory block is connected to the input of the decoder and the information input of the first register, the output of the first register is connected to the first input of the OR element and the information input of the second memory block, the output of the second memory block is connected It is connected to the second input of the OR element, the output of which is connected to the information input of the digital-to-analog converter, the output of which is connected to the information input of the switch, the first output of the decoder is connected to the control input of the first register, the second output - to the control input of the comparison blocks, the third output through the second register with the first information input of the comparison block, the output of the comparison block with the first control input of the second memory block and the first input of the AND element, the output of the AND element with the second control input of the second the memory block and the control input of the counter, the counter output — with the second information input of the comparison unit, the first output of the clock — with the counting input of the counter, the control input of the first memory block and the third control input of the second memory block, the second, third and the fourth outputs of the chroniser are respectively connected with the second input of the AND element, the control input of the digital-to-analog converter and the control input of the switch; the outputs of the switch are the outputs of the device.